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Alessandra Nardi
Observed name:
A. Nardi
Institution:
Synopsys (United States)
Observed institutions:
University of Padua,
Synopsys (United States),
STMicroelectronics (Italy),
Cadence Design Systems (United States),
University of California, Berkeley
ORCID:
0009-0001-4640-5017
Observed ORCID:
0009-0001-4640-5017
OpenAlex ID:
A5087339623
Functional safety methodologies for automotive applications
2017
·
Alessandra Nardi
, Antonino Armato
·
International Conference on Computer Aided Design
·
74
Analysis of the impact of process variations on clock skew
2000
·
S. Zanella
, A. Nardi
, et al.
·
IEEE Transactions on Semiconductor Manufacturing
·
57
Impact of unrealistic worst case modeling on the performance of VLSI circuits in deep sub-micron CMOS technologies
2002
·
A. Nardi
, A. Neviani
, et al.
·
International Workshop on Statistical Metrology (IWSM)
·
31
Logic synthesis for manufacturability
2004
·
A. Nardi
, A.L. Sangiovanni-Vincentelli
·
IEEE Design & Test of Computers
·
29
Degradation mechanisms in polysilicon emitter bipolar junction transistors for digital applications
2000
·
Loris Vendrame
, Paolo Pavan
, et al.
·
Microelectronics Reliability
·
29
Impact of unrealistic worst case modeling on the performance of VLSI circuits in deep submicron CMOS technologies
1999
·
A. Nardi
, A. Neviani
, et al.
·
IEEE Transactions on Semiconductor Manufacturing
·
26
Synthesis for manufacturability: a sanity check
2004
·
A. Nardi
, Alberto Sangiovanni‐Vincentelli
·
22
Design-For-Safety For Automotive IC Design: Challenges And Opportunities
2019
·
Alessandra Nardi
, Samir Camdzic
, et al.
·
Custom Integrated Circuits Conference
·
21
Analysis of the impact of intra-die variance on clock skew
2003
·
S. Zanella
, A. Nardi
, et al.
·
International Workshop on Statistical Metrology (IWSM)
·
6
Hot-carrier degradation and oxide charge build-up in self-aligned etched-polysilicon npn bipolar transistors
1997
·
A. Neviani
, P. Pavan
, et al.
·
IEEE Transactions on Electron Devices
·
6
Use of statistical timing analysis on real designs
2007
·
A. Nardi
, E. Tuncer
, et al.
·
5
Use of Statistical Timing Analysis on Real Designs
2007
·
A. Nardi
, E. Tuncer
, et al.
·
Design, Automation, and Test in Europe
·
4
Realistic worst-case modeling by performance level principal component analysis
2002
·
A. Nardi
, A. Neviani
, et al.
·
International Symposium on Quality Electronic Design (ISQED)
·
2
Statistical Analysis of Architectural Vulnerability Factor for Soft Errors
2026
·
Alessandra Nardi
, David Kingston
, et al.
·
IEEE International On-Line Testing Symposium (IOLTS)
Early Functional Safety and PPA Evaluation for Faster Digital Design Development
2026
·
Michelangelo Bartolomucci
, David Kingston
, et al.
·
IEEE Access
Early Functional Safety and PPA Evaluation of Digital Designs
2025
·
Michelangelo Bartolomucci
, David Kingston
, et al.
·
Design, Automation, and Test in Europe
PDF
Impact of Unrealistic Worst Case Modeling on the Technologies Perf'orr/iance of Vlsi Circuits in Deep Sub-micron Cmos
2004
·
A. Nardi
, A. Neviani
, et al.
Performance-aware reliability optimization for digital designs
·
Michelangelo Bartolomucci
, Uyen Tran
, et al.
·
PORTO@Iris
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Works count:
18
Citation count:
312
H-index:
8
I10-index:
8
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