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Hsiang-Hui Chang

Observed name: Hsiang-hui Chang
Institution: MediaTek (Taiwan)
OpenAlex ID: A5100809620
A wide-range delay-locked loop with a fixed latency of one clock cycle
2002 · Hsiang-Hui Chang, Jyh-Woei Lin, et al. · IEEE Journal of Solid-State Circuits · 158
A spread-spectrum clock generator with triangular modulation
2003 · Hsiang-Hui Chang, I-Hui Hua, et al. · IEEE Journal of Solid-State Circuits · 112
A wide-range and fast-locking all-digital cycle-controlled delay-locked loop
2005 · Hsiang-Hui Chang, Shen-Iuan Liu · IEEE Journal of Solid-State Circuits · 79
A Digital Intensive Fractional-N PLL and All-Digital Self-Calibration Schemes
2009 · Ping-Ying Wang, Jing-Hong Conan Zhan, et al. · IEEE Journal of Solid-State Circuits · 60
A Fractional Spur-Free ADPLL with Loop-Gain Calibration and Phase-Noise Cancellation for GSM/GPRS/EDGE
2008 · Hsiang-Hui Chang, Ping-Ying Wang, et al. · Digest of technical papers/Digest of technical papers - IEEE International Solid-State Circuits Conference · 47
A SAW-Less GSM/GPRS/EDGE Receiver Embedded in 65-nm SoC
2011 · Chi-Yao Yu, Ivan Siu-Chuang Lu, et al. · IEEE Journal of Solid-State Circuits · 36
A low-jitter and precise multiphase delay-locked loop using shifted averaging VCDL
2003 · Hsiang-Hui Chang, Chih-Hao Sun, et al. · Digest of technical papers/Digest of technical papers - IEEE International Solid-State Circuits Conference · 28
A fast locking and low jitter delay-locked loop using DHDL
2003 · Hsiang-Hui Chang, Jyh-Woei Lin, et al. · IEEE Journal of Solid-State Circuits · 20
A Low-Current Digitally Predistorted Direct-Conversion Transmitter With 25% Duty-Cycle Passive Mixer
2014 · Manel Collados, HongLi Zhang, et al. · IEEE Transactions on Microwave Theory and Techniques · 13
A 1.6–880MHz synthesizable ADPLL in 0.13um CMOS
2008 · Hsiang-Hui Chang, Shang-Ming Lee, et al. · International Symposium on VLSI Design, Automation and Test · 11
An analog enhanced all digtial RF fractional-N PLL with self-calibrated capability
2008 · Ping-Ying Wang, Jing-Hong Conan Zhan, et al. · Custom Integrated Circuits Conference · 10
A 65-nm GSM/GPRS/EDGE SoC With Integrated BT/FM
2013 · Tzung-Han Wu, Hsiang-Hui Chang, et al. · IEEE Journal of Solid-State Circuits · 9
A 320fs-RMS-jitter and 300kHz-BW all-digital fractional-N PLL with self-corrected TDC and fast temperature tacking loop for WiMax/WLAN 11n
2009 · Hsiang-Hui Chang, Chia-Huang Fu, et al. · Symposium on VLSI Circuits · 9
A HSPA+/WCDMA/EDGE 40nm Modem SoC with embedded RF transceiver supporting RX diversity
2014 · Jon Strange, Hsiang-Hui Chang, et al. · Digest of papers - IEEE Radio Frequency Integrated Circuits Symposium · 8
A fractional spur reduction technique for RF TDC-based all digital PLLs
2008 · Ping-Ying Wang, Hsiang-Hui Chang, et al. · European Solid-State Circuits Conference (ESSCIRC) · 7
A shifted-averaging VCO with precise multiphase outputs and low jitter operation
2004 · Hsiang-Hui Chang, Shang-Ping Chen, et al. · European Solid-State Circuits Conference (ESSCIRC) · 5
A low-current digitally predistorted 3G-4G transmitter in 40nm CMOS
2013 · Manel Collados, Hongli Zhang, et al. · Digest of papers - IEEE Radio Frequency Integrated Circuits Symposium · 4
A wide-range and fixed latency of one clock cycle delay-locked loop
2003 · Hsiang-Hui Chang, Jyh-Woei Lin, et al. · IEEE International Symposium on Circuits and Systems proceedings · 4
A 65nm GSM/GPRS/EDGE SoC with Integrated BT/FM
2012 · Chinq-Shiun Chiu, Hsiang-Hui Chang, et al. · Digest of papers - IEEE Radio Frequency Integrated Circuits Symposium · 3
A 10-mA Current and 1.1-μV Sensitivity Single-Chip FM Radio Receiver
2006 · Yung-Chun Lei, Tsung-Yao Lin, et al. · IEEE Asian Solid-State Circuits Conference (A-SSCC) · 3
A 0.8 V switched-opamp bandpass ΔΣ modulator using a two-path architecture
2003 · Hsiang-Hui Chang, Shang-Ping Chen, et al. · AP-ASIC'99. First IEEE Asia Pacific Conference on ASICs (Cat. No.99EX360) · 3
A 1.22/6.7 ppm/°C VCO with frequency-drifting compensator in 60 nm CMOS
2011 · Lan-Chou Cho, Hsiang-Hui Chang, et al. · IEEE Asian Solid-State Circuits Conference (A-SSCC) · 2
A transfer-curve-folded DCO in 0.13μm CMOS
2008 · Jing-Hong Conan Zhan, Hsiang-Hui Chang, et al. · Digest of papers - IEEE Radio Frequency Integrated Circuits Symposium · 2
A Calibrated Pulse Generator for Impuljse-radio UWB Applications
2005 · Che-fu Liang, Shih-tsai Liu, et al. · IEEE Asian Solid-State Circuits Conference (A-SSCC) · 1
Low jitter Butterworth delay-locked loops
2004 · Hsiang-Hui Chang, Chih-Hao Sun, et al. · Symposium on VLSI Circuits · 1
Works count: 32
Citation count: 636
H-index: 10
I10-index: 11
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