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Chung-Cheng Wu

Observed names: C. C. Wu, C.C. Wu, Chuan‐Yung Wu
ORCID: 0009-0002-2495-2535
Observed ORCID: 0009-0002-2495-2535
OpenAlex ID: A5102854725
A 20nm 112Mb SRAM in High-к metal-gate with assist circuitry for low-leakage and low-VMIN applications
2013 · J. Chang, Yen-Huei Chen, et al. · Digest of technical papers/Digest of technical papers - IEEE International Solid-State Circuits Conference · 69
Leakage scaling in deep submicron CMOS for SoC
2002 · Yo-Sheng Lin, Chung-Cheng Wu, et al. · IEEE Transactions on Electron Devices · 65
A 0.13 μm CMOS technology with 193 nm lithography and Cu/low-k for high performance applications
2002 · K.K. Young, S.Y. Wu, et al. · Technical digest - International Electron Devices Meeting/Technical digest · 51
65nm CMOS high speed, general purpose and low power transistor technology for high volume foundry application
2004 · S.K.H. Fung, H.T. Huang, et al. · Symposium on VLSI Technology · 47
A 90-nm CMOS device technology with high-speed, general-purpose, and low-leakage transistors for system on chip applications
2003 · C.C. Wu, Y.K. Leung, et al. · Technical digest - International Electron Devices Meeting/Technical digest · 46
Demonstration of scaled Ge p-channel FinFETs integrated on Si
2012 · M. J. H. van Dal, G. Vellianitis, et al. · Technical digest - International Electron Devices Meeting/Technical digest · 43
A highly scaled, high performance 45 nm bulk logic CMOS technology with 0.242 μm2 SRAM cell
2007 · Kuan-Lun Cheng, C. C. Wu, et al. · Technical digest - International Electron Devices Meeting/Technical digest · 37
A Constant-Mobility Method to Enable MOSFET Series-Resistance Extraction
2007 · Da-Wen Lin, Ming-Lung Cheng, et al. · IEEE Electron Device Letters · 36
Flow and Heat Transfer Characteristics Inside Packed and Fluidized Beds
1998 · C. C. Wu, G. J. Hwang · ASME Journal of Heat and Mass Transfer · 36
A 0.18 /spl mu/m CMOS logic technology with dual gate oxide and low-k interconnect for high-performance and low-power applications
1999 · C.H. Diaz, K.L. Young, et al. · Symposium on VLSI Technology · 34
Monolayer-MoS 2 Stacked Nanosheet Channel with C-type Metal Contact
2023 · Yun-Yan Chung, Wei-Sheng Yun, et al. · Technical digest - International Electron Devices Meeting/Technical digest · 29
Status and Performance of Integration Modules Toward Scaled CMOS with Transition Metal Dichalcogenide Channel
2023 · Ang-Sheng Chou, Ching-Hao Hsu, et al. · Technical digest - International Electron Devices Meeting/Technical digest · 27
Adsorbing colloid flotation of heavy metal ions with activators
1988 · Shang-da Huang, Tswei-Ping Wu, et al. · Journal of Colloid and Interface Science · 21
Scaled contact length with low contact resistance in monolayer 2D channel transistors
2023 · Wen-Chia Wu, Terry Y.T. Hung, et al. · IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits) · 20
State-of-the-art RF/analog foundry technology
2003 · J.C.H. Lin, T.H. Yeh, et al. · IEEE Bipolar/BiCMOS Circuits and Technology Meeting (BCTM) · 19
Top-Gated P-MOSFET with CVD-Grown WSe2 Channels via Self-Aligned WOx Conversion for Spacer Doping
2025 · Meng-Zhan Li, Terry Y. T. Hung, et al. · Nano Letters · 18
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On the Extreme Scaling of Transistors with Monolayer MOS2 Channel
2024 · Wen-Chia Wu, Terry Y.T. Hung, et al. · IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits) · 18
Comprehensive Physics Based TCAD Model for 2D MX2 Channel Transistors
2022 · D. Mahaveer Sathaiya, Terry Y.T. Hung, et al. · Technical digest - International Electron Devices Meeting/Technical digest · 16
Comprehensive Study of Contact Length Scaling Down to 12 nm With Monolayer MoS 2 Channel Transistors
2023 · Wen-Chia Wu, Terry Y. T. Hung, et al. · IEEE Transactions on Electron Devices · 13
A Novel Method of MOSFET Series Resistance Extraction Featuring Constant Mobility Criteria and Mobility Universality
2010 · Da-Wen Lin, Ming-Lung Cheng, et al. · IEEE Transactions on Electron Devices · 13
Cost and power/performance optimized 20nm SoC technology for advanced mobile devices
2014 · G. Nallapati, J. Zhu, et al. · Symposium on VLSI Technology · 8
Extended 0.13 μm CMOS technology for the ultra high-speed and MS/RF application segments
2003 · C.S. Chang, C.P. Chao, et al. · Symposium on VLSI Technology · 7
Device properties in 90 nm and beyond and implications on circuit design
2004 · C.H. Diaz, K.H. Fung, et al. · Technical digest - International Electron Devices Meeting/Technical digest · 6
An Electrical Failure Analysis (EFA) Flow to Quantitatively Identify Invisible Defect on Individual Transistor: Using the Characterization of Random Dopant Fluctuation (RDF) as an Example
2018 · J.H. Lee, Y.M. Shcu, et al. · IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA) · 4
A seamless handoff scheme for IEEE 802.11 wireless networks
2011 · Yun‐Sheng Yen, Ruay‐Shiung Chang, et al. · Wireless Communications and Mobile Computing · 4
Works count: 30
Citation count: 698
H-index: 17
I10-index: 20
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