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Kuan-Cheng Su

Observed name: Kuan-cheng Su
Observed institution: United Microelectronics (Taiwan)
OpenAlex ID: A5103551482
Novel input ESD protection circuit with substrate-triggering technique in a 0.25-μm shallow-trench-isolation CMOS technology
2002 · Ming-Dou Ker, Tung-Yang Chen, et al. · IEEE International Symposium on Circuits and Systems proceedings · 28
Latch-up free ESD protection design with SCR structure in advanced CMOS technology
2011 · Chang-Tzu Wang, Tien-Hao Tang, et al. · IEEE International Reliability Physics Symposium proceedings · 10
High-robust ESD protection structure with embedded SCR in high-voltage CMOS process
2008 · Tai-Hsiang Lai, Ming-Dou Ker, et al. · IEEE International Reliability Physics Symposium proceedings · 10
ESD protection design with lateral DMOS transistor in 40-V BCD technology
2010 · Chang-Tzu Wang, Ming-Dou Ker, et al. · IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA) · 6
Self-Heating p-Channel Metal–Oxide–Semiconductor Field-Effect Transistors for Reliability Monitoring of Negative-Bias Temperature Instability
2007 · Ting-Kuo Kang, Chi-Shiun Wang, et al. · Japanese Journal of Applied Physics · 6
Design of High-Voltage-Tolerant Power-Rail ESD Clamp Circuit in Low-Voltage CMOS Processes
2007 · Ming-Dou Ker, Chang-Tzu Wang, et al. · IEEE International Reliability Physics Symposium proceedings · 6
Effects of Delay Time and AC Factors on Negative Bias Temperature Instability of PMOSFETs
2006 · Jih-san Li, Main-gwo Chen, et al. · IEEE International Integrated Reliability Workshop final report · 5
Design of modified ESD protection structure with low-trigger and high-holding voltage in embedded high voltage CMOS process
2011 · Tai-Hsiang Lai, Lu-An Chen, et al. · IEEE International Reliability Physics Symposium proceedings · 4
Optimization of PESD implant design for ESD robustness of 5V drain-back N-LDMOSFET
2016 · Chun Chiang, Ping-Chen Chang, et al. · IEEE International Reliability Physics Symposium proceedings · 3
ESD Robustness of 40-V CMOS Devices With/Without Drift Implant
2006 · Wei-jen Chang, Ming-dou Ker, et al. · IEEE International Integrated Reliability Workshop final report · 3
Ultra-Fast Negative Bias Temperature Instability Monitoring and End-of-Life Projection
2006 · Chi-shiun Wang, Wen-chun Chang, et al. · IEEE International Integrated Reliability Workshop final report · 3
Low-trigger ESD protection design with latch-up immunity for 5-V CMOS application by drain engineering
2017 · Chun Chiang, Ping-Chen Chang, et al. · IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA) · 2
Latch-up issue of drain metal connection split in test circuit with 3D TCAD simulation analysis in CMOS application
2019 · Chun Chiang, Ping-Chen Chang, et al. · Solid State Electronics Letters · 1
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A novel high level ESD FDNSCR with drain side engineering in PMIC application
2015 · Yi-Ning He, Jhih-Ming Wang, et al. · IEEE International Reliability Physics Symposium proceedings · 1
ESD protection design with adjustable snapback behavior for 5-V application in 100nm CMOS process
2013 · Chang-Tzu Wang, Yu-Chun Chen, et al. · IEEE International Reliability Physics Symposium proceedings · 1
The modified P+ electrode layout schemes to enhance esd robustness of SCR structure for PMIC applications
2011 · Lu-An Chen, Chang-Tzu Wang, et al. · IEEE International Reliability Physics Symposium proceedings · 1
Comprehensive hot carrier mechanism investigation of 40V LDNMOS transistor
2007 · Yi-Chun Wang, Yi-Pin Chen, et al. · IEEE International Integrated Reliability Workshop final report · 1
Lower trigger voltage design for ESD protection device applied in PMIC application
2014 · Yi-Ning He, Lu-An Chen, et al. · IEEE International Reliability Physics Symposium proceedings
Low-leakage electrostatic discharge protection circuit in 65-nm fully-silicided CMOS technology
2009 · Chang-Tzu Wang, Ming-Dou Ker, et al. · IEEE International Conference on IC Design and Technology (ICICDT)
The Impact of N-Drift Implant on ESD Robustness of High-Voltage NMOS with Embedded SCR Structure in 40-V CMOS Process
2007 · Wei-Jen Chang, Ming-Dou Ker, et al. · IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA)
Works count: 20
Citation count: 91
H-index: 6
I10-index: 3
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