Author

Masaaki Kinugawa

Observed names: M. Kinugawa, M.Kinugawa

OpenAlex ID: A5108076531

A 0.9-V, 150-MHz, 10-mW, 4 mm/sup 2/, 2-D discrete cosine transform core processor with variable threshold-voltage (VT) scheme

1996 · T. Kuroda, T. Fujita, et al. · IEEE Journal of Solid-State Circuits · 475

Future perspective and scaling down roadmap for RF CMOS

1999 · E. Morifuji, H.S. Momose, et al. · Symposium on VLSI Technology · 99

Power-supply voltage impact on circuit performance for half and lower submicrometer CMOS LSI

1990 · M. Kakumu, M. Kinugawa · IEEE Transactions on Electron Devices · 56

Choice of power-supply voltage for half-micrometer and lower submicrometer CMOS devices

1990 · M. Kakumu, M. Kinugawa, et al. · IEEE Transactions on Electron Devices · 41

Low-resistivity poly-metal gate electrode durable for high-temperature processing

1996 · Y. Akasaka, S. Suehiro, et al. · IEEE Transactions on Electron Devices · 32

Future perspective and scaling down roadmap for RF CMOS

2003 · E. Morifuji, H.S. Momose, et al. · Symposium on VLSI Circuits · 30

Anomalous hot-carrier induced degradation in very narrow channel nMOSFETs with STI structure

2002 · M. Nishigohri, K. Ishimaru, et al. · Technical digest - International Electron Devices Meeting/Technical digest · 28

Effects of silicon surface orientation on submicron CMOS devices

1985 · M. Kinugawa, M. Kakumu, et al. · Technical digest - International Electron Devices Meeting/Technical digest · 26

Submicron MLDO NMOSFETs for 5V Operation

1985 · Masaaki Kinugawa, M. Kakumu, et al. · Symposium on VLSI Technology · 18

Reliability and performance of submicron LDD NMOSFET's with buried As n-impurity profiles

1985 · H.R. Grinolds, M. Kinugawa, et al. · Technical digest - International Electron Devices Meeting/Technical digest · 18

Power supply voltage for future CMOS VLSI in half and sub micrometer

1986 · M. Kakumu, M. Kinugawa, et al. · Technical digest - International Electron Devices Meeting/Technical digest · 15

High performance MIM capacitor for RF BiCMOS/CMOS LSIs

2003 · T. Yoshitomi, Y. Ebuchi, et al. · IEEE Bipolar/BiCMOS Circuits and Technology Meeting (BCTM) · 14

Drain structure optimization for highly reliable deep submicrometer n-channel MOSFET

1994 · F. Matsuoka, K. Kasai, et al. · IEEE Transactions on Electron Devices · 14

A 4-Mb CMOS SRAM with a PMOS thin-film-transistor load cell

1990 · T. Ootani, S. Hayakawa, et al. · IEEE Journal of Solid-State Circuits · 14

Improvement of 1/f noise by using VHP (vertical high pressure) oxynitride gate insulator for deep-sub micron RF and analog CMOS

1999 · H. Kimijima, T. Ohguro, et al. · Symposium on VLSI Technology · 13

1-Mbit virtually static RAM

1986 · K. Nogami, T. Sakurai, et al. · IEEE Journal of Solid-State Circuits · 10

TFT (thin film transistor) cell technology for 4 Mbit and more high density SRAMs

1990 · M. Kinugawa, M. Kakumu, et al. · Symposium on VLSI Technology · 9

Submicron 3D Surface-Orientation-Optimized CMOS Technology

1986 · Masaaki Kinugawa, M. Kakumu, et al. · Symposium on VLSI Technology · 9

A 36ns 1Mbit Pseudo SRAM with VSRAM mode

1987 · Takayasu Sakurai, K. Sawada, et al. · Symposium on VLSI Circuits · 8

VLSI circuit reliability under AC hot-carrier stress

1987 · K. Nogami, K. Sawada, et al. · Symposium on VLSI Circuits · 8

A 1 mu A retention 4 Mb SRAM with a thin-film-transistor load cell

1990 · S. Hayakawa, M. Kakumu, et al. · Digest of technical papers/Digest of technical papers - IEEE International Solid-State Circuits Conference · 6

A 30- mu A data-retention pseudostatic RAM with virtually static RAM mode

1988 · K. Sawada, T. Sakurai, et al. · IEEE Journal of Solid-State Circuits · 6

A 1Mb virtually SRAM

1986 · T. Sakurai, K. Sawada, et al. · Digest of technical papers/Digest of technical papers - IEEE International Solid-State Circuits Conference · 6

Cell technology directions for advanced MPUs and other memory-embedded logic devices

2002 · M. Kinugawa, M. Kakumu · Technical digest - International Electron Devices Meeting/Technical digest · 4

W/WNx/poly-Si gate technology for future high speed deep submicron CMOS LSIs

2002 · K. Kasai, Y. Akasaka, et al. · Technical digest - International Electron Devices Meeting/Technical digest · 4

Works count: 43

Citation count: 989

H-index: 14

I10-index: 16