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K. Imamiya

Observed names: K.-I. Imamiya, K.I. Imamiya, Koji Imamiya
Institution: Toshiba (Japan)
OpenAlex ID: A5108839389
A 5-V-only operation 0.6- mu m flash EEPROM with row decoder scheme in triple-well structure
1992 · A. Umezawa, S. Atsumi, et al. · IEEE Journal of Solid-State Circuits · 147
A 70 nm 16 Gb 16-Level-Cell NAND flash Memory
2008 · N. Shibata, H. Maejima, et al. · IEEE Journal of Solid-State Circuits · 81
A negative V/sub th/ cell architecture for highly scalable, excellently noise-immune, and highly reliable NAND flash memories
1999 · K. Takeuchi, S. Satoh, et al. · IEEE Journal of Solid-State Circuits · 32
A 130-mm/sup 2/, 256-Mbit NAND flash with shallow trench isolation technology
1999 · K. Imamiya, Y. Sugiura, et al. · IEEE Journal of Solid-State Circuits · 30
A source-line programming scheme for low-voltage operation NAND flash memories
2000 · K. Takeuchi, S. Satoh, et al. · IEEE Journal of Solid-State Circuits · 26
A 125-mm/sup 2/ 1-Gb NAND flash memory with 10-MByte/s program speed
2002 · K. Imamiya, H. Nakamura, et al. · IEEE Journal of Solid-State Circuits · 21
A 35 ns cycle time 3.3 V only 32 Mb NAND flash EEPROM
1995 · Y. Iwata, K. Imamiya, et al. · IEEE Journal of Solid-State Circuits · 20
A 35 ns-cycle-time 3.3 V-only 32 Mb NAND flash EEPROM
2002 · K. Imamiya, Y. Iwata, et al. · Digest of technical papers/Digest of technical papers - IEEE International Solid-State Circuits Conference · 16
A negative Vth cell architecture for highly scalable, excellently noise immune and highly reliable NAND flash memories
2002 · K. Takeuchi, S. Satoh, et al. · Symposium on VLSI Circuits · 15
A 4-Mbit CMOS EPROM
1987 · N. Ohtsuka, S. Tanaka, et al. · IEEE Journal of Solid-State Circuits · 15
A 62ns 16Mb CMOS EPROM With Address Transition Detection Technique
1991 · N. Ohtsuka, J. Miyamoto, et al. · Digest of technical papers/Digest of technical papers - IEEE International Solid-State Circuits Conference · 11
A novel sense amplifier for flexible voltage operation NAND flash memories
2002 · H. Nakamura, J. Miyamoto, et al. · Symposium on VLSI Circuits · 10
A source-line programming scheme for low voltage operation NAND flash memories
2003 · K. Takeuchi, S. Satoh, et al. · Symposium on VLSI Circuits · 8
A 16-ns 1-Mb CMOS EPROM
1990 · M. Kuriyama, S. Atsumi, et al. · IEEE Journal of Solid-State Circuits · 7
A 5 V-only 0.6 mu m flash EEPROM with row decoder scheme in triple-well structure
2003 · M. Kuriyama, S. Atsumi, et al. · Digest of technical papers/Digest of technical papers - IEEE International Solid-State Circuits Conference · 6
A 130 mm/sup 2/ 256 Mb NAND flash with shallow trench isolation technology
2003 · K. Imamiya, Y. Sugiura, et al. · Digest of technical papers/Digest of technical papers - IEEE International Solid-State Circuits Conference · 5
A 68-ns 4-Mbit CMOS EPROM with high-noise-immunity design
1990 · K. Imamiya, J. Miyamoto, et al. · IEEE Journal of Solid-State Circuits · 5
A 125mm/sup 2/ 1Gb NAND flash memory with 10MB/s program throughput
2005 · H. Nakamura, K. Imamiya, et al. · Digest of technical papers/Digest of technical papers - IEEE International Solid-State Circuits Conference · 4
A 60 ns access 32 kByte 3-transistor flash for low power embedded applications
2002 · T. Ikehashi, J. Noda, et al. · Symposium on VLSI Circuits · 4
A 125 mm/sup 2/ 1Gb NAND flash memory with 10 MB/s program throughput
2003 · H. Nakamura, K. Imamiya, et al. · Digest of technical papers/Digest of technical papers - IEEE International Solid-State Circuits Conference · 3
A Study of Electrophotography Process for Manufacturing Printed Circuit Board
2004 · Hideo Aoki, Naoko Yamaguchi, et al. · Technical programs and proceedings/Technical program and proceedings · 2
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Design methodology of a robust ESD protection circuit for STI process 256 Mb NAND memory
2003 · T. Ikehashi, K. Imamiya, et al. · Electrical Overstress/Electrostatic Discharge Symposium · 2
A sophisticated bit-by-bit verifying scheme for NAND EEPROMs
2002 · K. Sakui, K. Kanda, et al. · Symposium on VLSI Circuits · 2
A 16 ns 1 Mb CMOS EPROM
1990 · S. Atsumi, M. Kuriyama, et al. · Digest of technical papers/Digest of technical papers - IEEE International Solid-State Circuits Conference · 2
Optimum redundancy design for new-generation EPROMs based on yield analysis of previous generation
2003 · K. Imamiya, J. Miyamoto, et al. · IEEE VLSI Test Symposium (VTS) · 1
Works count: 30
Citation count: 476
H-index: 11
I10-index: 12
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