A sophisticated bit-by-bit verifying scheme for NAND EEPROMs
Year: 2002
Type: conference-paper
Source: Symposium on VLSI Circuits
Authors: K. Sakui, K. Kanda, H. Nakamura, K. Imamiya, J. Miyamoto
Institution: Toshiba (Japan)
Language: English
Subfield: Electrical and Electronic Engineering
Field: Engineering
Domain: Physical Sciences
Open Access status: closed
OpenAlex ID: W2139151515
