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J. Miyamoto

Observed name: J.-I. Miyamoto
Institution: Toshiba (Japan)
OpenAlex ID: A5111676830
A 120-mm/sup 2/ 64-Mb NAND flash memory achieving 180 ns/Byte effective program speed
1997 · Jin-Ki Kim, K. Sakui, et al. · IEEE Journal of Solid-State Circuits · 27
A 35 ns cycle time 3.3 V only 32 Mb NAND flash EEPROM
1995 · Y. Iwata, K. Imamiya, et al. · IEEE Journal of Solid-State Circuits · 20
A new technique for measuring threshold voltage distribution in flash EEPROM devices
2002 · T. Himeno, N. Matsukawa, et al. · IEEE International Conference on Microelectronic Test Structures (ICMTS) · 17
A high-speed 64K CMOS RAM with bipolar sense amplifiers
1984 · J.-I. Miyamoto, S. Saito, et al. · IEEE Journal of Solid-State Circuits · 17
A 35 ns-cycle-time 3.3 V-only 32 Mb NAND flash EEPROM
2002 · K. Imamiya, Y. Iwata, et al. · Digest of technical papers/Digest of technical papers - IEEE International Solid-State Circuits Conference · 16
A 4-Mbit CMOS EPROM
1987 · N. Ohtsuka, S. Tanaka, et al. · IEEE Journal of Solid-State Circuits · 15
A 1.0µm N-well CMOS/Bipolar technology for VLSI circuits
1983 · J. Miyamoto, S. Saitoh, et al. · Technical digest - International Electron Devices Meeting/Technical digest · 15
An experimental 5-V-only 256-kbit CMOS EEPROM with a high-performance single-polysilicon cell
1986 · J. Miyamoto, J. Tsujimoto, et al. · IEEE Journal of Solid-State Circuits · 14
A 28ns CMOS SRAM with bipolar sense amplifiers
1984 · J. Miyamoto, S. Saitoh, et al. · Digest of technical papers/Digest of technical papers - IEEE International Solid-State Circuits Conference · 14
1.0-µm n-well CMOS/bipolar technology
1985 · H. Momose, H. Shibata, et al. · IEEE Transactions on Electron Devices · 13
A 62ns 16Mb CMOS EPROM With Address Transition Detection Technique
1991 · N. Ohtsuka, J. Miyamoto, et al. · Digest of technical papers/Digest of technical papers - IEEE International Solid-State Circuits Conference · 11
A novel sense amplifier for flexible voltage operation NAND flash memories
2002 · H. Nakamura, J. Miyamoto, et al. · Symposium on VLSI Circuits · 10
1.0-/spl mu/m n-Well CMOS/Bipolar Technology
1985 · H. Momose, H. Shibata, et al. · IEEE Journal of Solid-State Circuits · 9
A 120 mm/sup 2/ 64 Mb NAND flash memory achieving 180 ns/byte effective program speed
2002 · Jin-Ki Kim, Koji Sakui, et al. · Symposium on VLSI Circuits · 7
Application of polycrystalline silicon load for high performance bipolar memory
1980 · J. Miyamoto, K. Shinada, et al. · Technical digest - International Electron Devices Meeting/Technical digest · 6
Effects of gate geometry on propagation delay of integrated injection logic (I/sup 2/L)
1978 · S. Shinozaki, K. Shinada, et al. · IEEE Journal of Solid-State Circuits · 6
Role of the external n-p-n base region on the switching speed of integrated injection logic (I/sup 2/L)
1977 · S. Shinozaki, T. Iizuka, et al. · IEEE Journal of Solid-State Circuits · 6
A 68-ns 4-Mbit CMOS EPROM with high-noise-immunity design
1990 · K. Imamiya, J. Miyamoto, et al. · IEEE Journal of Solid-State Circuits · 5
A single-chip LSI high-speed functional tester
1987 · J. Miyamoto, M.A. Horowitz · IEEE Journal of Solid-State Circuits · 3
A sophisticated bit-by-bit verifying scheme for NAND EEPROMs
2002 · K. Sakui, K. Kanda, et al. · Symposium on VLSI Circuits · 2
A High Density Single-Poly Si Structure Eeprom with LB (Lowered Barrier Height) Oxide for VLSI's
1985 · N. Matsukawa, S. Morita, et al. · Symposium on VLSI Technology · 2
Optimum redundancy design for new-generation EPROMs based on yield analysis of previous generation
2003 · K. Imamiya, J. Miyamoto, et al. · IEEE VLSI Test Symposium (VTS) · 1
A quick address detection of an anomalous memory cell for flash EEPROM
2002 · T. Himeno, H. Hazama, et al. · IEEE International Conference on Microelectronic Test Structures (ICMTS) · 1
Quick address detection of anomalous memory cells in a flash memory test structure
1997 · T. Himeno, H. Hazama, et al. · IEEE Transactions on Semiconductor Manufacturing · 1
A single-chip functional tester
1987 · J. Miyamoto, M. Horowitz · Digest of technical papers/Digest of technical papers - IEEE International Solid-State Circuits Conference · 1
Works count: 28
Citation count: 239
H-index: 11
I10-index: 12
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