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Tien-Hao Tang

Observed names: T.H. Tang, Tien-hao Tang
OpenAlex ID: A5110257199
Low-leakage diode string designs using triple-well technologies for RF-ESD applications
2003 · Shiao-Shien Chen, Tung-Yang Chen, et al. · IEEE Electron Device Letters · 26
Hot carrier degradation in novel strained-Si nMOSFETs
2004 · M.F. Lu, S. Chiang, et al. · IEEE International Reliability Physics Symposium proceedings · 19
Using layout technique and direct-tunneling mechanism to promote DC performance of partially depleted SOI devices
2004 · Shiao-Shien Chen, Shiang Huang-Lu, et al. · IEEE Transactions on Electron Devices · 13
Latch-up free ESD protection design with SCR structure in advanced CMOS technology
2011 · Chang-Tzu Wang, Tien-Hao Tang, et al. · IEEE International Reliability Physics Symposium proceedings · 10
High-robust ESD protection structure with embedded SCR in high-voltage CMOS process
2008 · Tai-Hsiang Lai, Ming-Dou Ker, et al. · IEEE International Reliability Physics Symposium proceedings · 10
ESD protection design with lateral DMOS transistor in 40-V BCD technology
2010 · Chang-Tzu Wang, Ming-Dou Ker, et al. · IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA) · 6
Design of High-Voltage-Tolerant Power-Rail ESD Clamp Circuit in Low-Voltage CMOS Processes
2007 · Ming-Dou Ker, Chang-Tzu Wang, et al. · IEEE International Reliability Physics Symposium proceedings · 6
Characteristics of low-leakage deep-trench diode for ESD protection design in 0.18-μm SiGe BiCMOS process
2003 · Shiao-Shien Chen, Tung-Yang Chen, et al. · IEEE Transactions on Electron Devices · 6
Investigation of a SiGe HBT during ESD stress in a 0.18-μm SiGe BiCMOS process
2003 · Shiao-Shien Chen, Tung-Yang Chen, et al. · IEEE Electron Device Letters · 5
Design of modified ESD protection structure with low-trigger and high-holding voltage in embedded high voltage CMOS process
2011 · Tai-Hsiang Lai, Lu-An Chen, et al. · IEEE International Reliability Physics Symposium proceedings · 4
Investigation of ESD devices in 0.18 μm SiGe BiCMOS process
2003 · Shiao-Shien Chen, Tung-Yang Chen, et al. · IEEE International Reliability Physics Symposium proceedings · 4
Optimization of PESD implant design for ESD robustness of 5V drain-back N-LDMOSFET
2016 · Chun Chiang, Ping-Chen Chang, et al. · IEEE International Reliability Physics Symposium proceedings · 3
ESD Robustness of 40-V CMOS Devices With/Without Drift Implant
2006 · Wei-jen Chang, Ming-dou Ker, et al. · IEEE International Integrated Reliability Workshop final report · 3
Low-trigger ESD protection design with latch-up immunity for 5-V CMOS application by drain engineering
2017 · Chun Chiang, Ping-Chen Chang, et al. · IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA) · 2
Latch-up issue of drain metal connection split in test circuit with 3D TCAD simulation analysis in CMOS application
2019 · Chun Chiang, Ping-Chen Chang, et al. · Solid State Electronics Letters · 1
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A novel high level ESD FDNSCR with drain side engineering in PMIC application
2015 · Yi-Ning He, Jhih-Ming Wang, et al. · IEEE International Reliability Physics Symposium proceedings · 1
ESD protection design with adjustable snapback behavior for 5-V application in 100nm CMOS process
2013 · Chang-Tzu Wang, Yu-Chun Chen, et al. · IEEE International Reliability Physics Symposium proceedings · 1
The modified P+ electrode layout schemes to enhance esd robustness of SCR structure for PMIC applications
2011 · Lu-An Chen, Chang-Tzu Wang, et al. · IEEE International Reliability Physics Symposium proceedings · 1
ESD investigation of pn junction diodes in silicon-germanium heterojunction bipolar transistor
2003 · C.H. Chou, S.S. Chen, et al. · Electronics Letters · 1
Lower trigger voltage design for ESD protection device applied in PMIC application
2014 · Yi-Ning He, Lu-An Chen, et al. · IEEE International Reliability Physics Symposium proceedings
Low-leakage electrostatic discharge protection circuit in 65-nm fully-silicided CMOS technology
2009 · Chang-Tzu Wang, Ming-Dou Ker, et al. · IEEE International Conference on IC Design and Technology (ICICDT)
The Impact of N-Drift Implant on ESD Robustness of High-Voltage NMOS with Embedded SCR Structure in 40-V CMOS Process
2007 · Wei-Jen Chang, Ming-Dou Ker, et al. · IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA)
Reliability investigations on a unique direct-tunneling-induced high performance partially-depleted SOI PMOS device
2004 · Shiao-Shien Chen, Shiang Huang-Lu, et al. · IEEE International Reliability Physics Symposium proceedings
Works count: 23
Citation count: 122
H-index: 6
I10-index: 5
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