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Chih-Chang Hsieh
Observed name:
Chih Chang Hsieh
Institution:
Macronix International (Taiwan)
Observed institutions:
National Yang Ming Chiao Tung University,
Macronix International (China),
Macronix International (Taiwan)
OpenAlex ID:
A5111538188
Radically extending the cycling endurance of Flash memory (to > 100M Cycles) by using built-in thermal annealing to self-heal the stress-induced damage
2012
·
Hang-Ting Lue
, Pei-Ying Du
, et al.
·
Technical digest - International Electron Devices Meeting/Technical digest
·
60
Study of fast initial charge loss and it's impact on the programmed states Vt distribution of charge-trapping NAND Flash
2010
·
Chih-Ping Chen
, Hang-Ting Lue
, et al.
·
Technical digest - International Electron Devices Meeting/Technical digest
·
52
A highly scalable 8-layer Vertical Gate 3D NAND with split-page bit line layout and efficient binary-sum MiLC (Minimal Incremental Layer Cost) staircase contacts
2012
·
Shih-Hung Chen
, Hang-Ting Lue
, et al.
·
Technical digest - International Electron Devices Meeting/Technical digest
·
41
A 512Gb In-Memory-Computing 3D-NAND Flash Supporting Similar-Vector-Matching Operations on Edge-AI Devices
2022
·
Han-Wen Hu
, Wei-Chen Wang
, et al.
·
Digest of technical papers/Digest of technical papers - IEEE International Solid-State Circuits Conference
·
36
ICE: An Intelligent Cognition Engine with 3D NAND-based In-Memory Computing for Vector Similarity Search Acceleration
2022
·
Han-Wen Hu
, Wei-Chen Wang
, et al.
·
IEEE/ACM International Symposium on Microarchitecture (MICRO)
·
30
A novel double-density, single-gate vertical channel (SGVC) 3D NAND Flash that is tolerant to deep vertical etching CD variation and possesses robust read-disturb immunity
2015
·
Hang-Ting Lue
, Tzu-Hsuan Hsu
, et al.
·
Technical digest - International Electron Devices Meeting/Technical digest
·
26
Analog Computing in Memory (CIM) Technique for General Matrix Multiplication (GEMM) to Support Deep Neural Network (DNN) and Cosine Similarity Search Computing using 3D AND-type NOR Flash Devices
2022
·
Ming-Liang Wei
, Hang-Ting Lue
, et al.
·
Technical digest - International Electron Devices Meeting/Technical digest
·
23
A Monte Carlo simulation method to predict large-density NAND product memory window from small-array test element group (TEG) verified on a 3D NAND Flash test chip
2016
·
Chih-Chang Hsieh
, Hang-Ting Lue
, et al.
·
Symposium on VLSI Technology
·
23
A highly pitch scalable 3D vertical gate (VG) NAND flash decoded by a novel self-aligned independently controlled double gate (IDG) string select transistor (SSL)
2012
·
Chih-Ping Chen
, Hang-Ting Lue
, et al.
·
Symposium on VLSI Technology
·
23
In-Memory-Searching Architecture Based on 3D-NAND Technology with Ultra-high Parallelism
2020
·
Po-Hao Tseng
, Feng-Ming Lee
, et al.
·
Technical digest - International Electron Devices Meeting/Technical digest
·
22
Study of sub-30nm thin film transistor (TFT) charge-trapping (CT) devices for 3D NAND flash application
2009
·
Tzu-Hsuan Hsu
, Hang-Ting Lue
, et al.
·
Technical digest - International Electron Devices Meeting/Technical digest
·
22
A 3D Stackable DRAM: Capacitor-less Three-Wordline Gate-Controlled Thyristor (GCT) RAM with >40 μ A Current Sensing Window, >1010 Endurance, and 3-second Retention at Room Temperature
2022
·
Wei-Chen Chen
, Hang-Ting Lue
, et al.
·
Technical digest - International Electron Devices Meeting/Technical digest
·
16
A 128Gb (MLC)/192Gb (TLC) single-gate vertical channel (SGVC) architecture 3D NAND using only 16 layers with robust read disturb, long-retention and excellent scaling capability
2017
·
Hang-Ting Lue
, Pei-Ying Du
, et al.
·
Technical digest - International Electron Devices Meeting/Technical digest
·
16
A physics-based Quasi-2D model to understand the wordline (WL) interference effects of junction-free structure of 3D NAND and experimental study in a 3D NAND flash test chip
2017
·
Wei-Chen Chen
, Hang-Ting Lue
, et al.
·
Technical digest - International Electron Devices Meeting/Technical digest
·
15
Chip Demonstration of a High-Density (43Gb) and High-Search-Bandwidth (300Gb/s) 3D NAND Based In-Memory Search Accelerator for Ternary Content Addressable Memory (TCAM) and Proximity Search of Hamming Distance
2023
·
Chih-Chang Hsieh
, Hang-Ting Lue
, et al.
·
IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)
·
14
Z-Interference and Z-Disturbance in Vertical Gate-Type 3-D NAND
2016
·
Teng-Hao Elton Yeh
, Wei-Chen Chen
, et al.
·
IEEE Transactions on Electron Devices
·
14
On relaxing page program disturbance over 3D MLC flash memory
2015
·
Yu-Ming Chang
, Yung-Chun Li
, et al.
·
International Conference on Computer Aided Design
·
14
Study of the programming sequence induced back-pattern effect in split-page 3D vertical-gate (VG) NAND flash
2014
·
Wei-Chen Chen
, Hang-Ting Lue
, et al.
·
International Symposium on VLSI Technology, Systems and Applications (VLSI-TSA)
·
14
Device Characteristics of Single-Gate Vertical Channel (SGVC) 3D NAND Flash Architecture
2016
·
Chen-Jun Wu
, Hang-Ting Lue
, et al.
·
IEEE International Memory Workshop (IMW)
·
13
Memory Architecture of 3D Vertical Gate (3DVG) NAND Flash Using Plural Island-Gate SSL Decoding Method and Study of it's Program Inhibit Characteristics
2012
·
Kuo-Pin Chang
, Hang-Ting Lue
, et al.
·
IEEE International Memory Workshop (IMW)
·
13
A novel double-trapping BE-SONOS charge-trapping NAND flash device to overcome the erase saturation without using curvature-induced field enhancement effect or high-K (HK)/metal gate (MG) materials
2014
·
Hang-Ting Lue
, Roger Lo
, et al.
·
Technical digest - International Electron Devices Meeting/Technical digest
·
11
Study of the interference and disturb mechanisms of split-page 3D vertical gate (VG) NAND flash and optimized programming algorithms for multi-level cell (MLC) storage
2013
·
Chih-Chang Hsieh
, Hang-Ting Lue
, et al.
·
Symposium on VLSI Technology
·
11
Read Disturb Evaluations of 3D NAND Flash for Highly Read-Intensive Edge-Computing Inference Device for Artificial Intelligence Applications
2019
·
Pei-Ying Du
, Hang-Ting Lue
, et al.
·
IEEE International Memory Workshop (IMW)
·
10
Design innovations to optimize the 3D stackable vertical gate (VG) NAND flash
2012
·
Chun-Hsiung Hung
, Hang-Ting Lue
, et al.
·
Technical digest - International Electron Devices Meeting/Technical digest
·
10
NOR Flash-based Multilevel In-Memory-Searching Architecture for Approximate Computing
2022
·
Yu-Hsuan Lin
, Po-Hao Tseng
, et al.
·
IEEE International Memory Workshop (IMW)
·
9
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Works count:
36
Citation count:
581
H-index:
14
I10-index:
24
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