Author

Md. Badhesha

Observed names: MD Badhesha, MD. Badhesha, Md Badhesha

Observed institution: SR University

ORCID: 0009-0009-1989-3033

Observed ORCID: 0009-0009-1989-3033

OpenAlex ID: A5116232382

Performance Optimization of FIR Filters Using Approximate Multipliers

2025 · Aluvoju Vivek, Arun Sekar Rajasekaran, et al. · International Conference on Wireless Communications, Signal Processing and Networking (WiSPNET) · 3

Design and Analysis of Compressor Using Approximate Full Adders for Future Low power Electronics

2025 · MD Badhesha, Arun Sekar Rajasekaran, et al. · International Conference on Wireless Communications, Signal Processing and Networking (WiSPNET) · 1

Reliability Study of Thermal Inversion Effect on Ultra Low Power Array Multiplier Using 7nm FinFET Technology for 3D IC Integration

2026 · Shilagani Shivaprasad, MD Badhesha, et al. · IEEE International Conference on Interdisciplinary Approaches in Technology and Management for Social Innovation (IATMSI)

Performance Analysis of a Race Reduced Data Flip Flop Under Wide Thermal Variations for Future High-Speed Counters and Prescalers

2026 · Shilagani Shivaprasad, Daddanala Nagavarun, et al. · IEEE International Conference on Interdisciplinary Approaches in Technology and Management for Social Innovation (IATMSI)

An Efficient Certificateless Signature verification scheme using Bilinear pairing for VANETs

2025 · Md Badhesha, Arun Sekar Rajasekaran, et al. · International Conference on Research in Computational Intelligence and Communication Networks (ICRCICN)

Power-Delay Trade-Off Analysis of Low-Voltage Flip-Flop Architectures for Energy-Constrained Applications

2025 · Pandrala Pravardhan, Yarra Sridevi, et al. · IEEE Conference on Information and Communication Technology (CICT)

A SPICE Investigation on Signed and Unsigned Multipliers for Hardware Cryptography Using Hybrid Pass Static CMOS Full Adders

2025 · Ponnaboina Charan Sai, Shilagani Shivaprasad, et al. · IEEE International Conference on Intelligent Signal Processing and Effective Communication Technologies (INSPECT)

A SPICE Simulation Study of Stacked Inverters and Transistors Type D Flip-Flop Designs with 16-nm CMOS Technology

2025 · Md. Badhesha, J. Ajayan, et al. · IEEE International Conference on Green Industrial Electronics and Sustainable Technologies (GIEST)

Reliability Investigation of High Performance Nanoscale Dual Edge Triggered (DET) TSPC-D-Flip Flops for Future Low Power Electronics

2025 · Md. Badhesha, Motla Sathwika, et al. · IEEE International Conference on Green Industrial Electronics and Sustainable Technologies (GIEST)

Reliability Study of Nano Scale Baugh Wooley Multiplier for Future Digital Signal Processing Applications

2025 · Janamanchi Rathna Koushal, Md Badhesha, et al. · Devices for Integrated Circuit (DevIC)

Temperature‐Driven Performance and Reliability Trade‐Offs in 7 nm FinFET‐Based Dynamic Comparators

2025 · MD Badhesha, J. Ajayan, et al. · IET Circuits Devices & Systems

PDF

High Performance Array Multiplier Implemented Using Full Swing Adders for Fast Computations in Digital Signal Processing and Neural Networks

2024 · Md. Badhesha, J. Ajayan, et al. · International Conference on Emerging Frontiers in Electrical and Electronic Technologies (ICEFEET)

Works count: 12

Citation count: 4

H-index: 1

I10-index: