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Author

Syeda Hurmath Juveria

Institution: SR University
Observed institution: SR University
ORCID: 0009-0002-4433-9922
Observed ORCID: 0009-0002-4433-9922
OpenAlex ID: A5116295903
A Review of Performance and Reliability Issues in D Flip‐Flops for Future Artificial Intelligence and Internet of Things Applications
2025 · Syeda Hurmath Juveria, R. Shashank, et al. · IET Circuits Devices & Systems · 2
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Design of a High-Speed Bit-length-Independent FinFET-based Hybrid Carry Look Ahead-Carry Skip Adder for Future Signal Processing Systems
2026 · B. Sandhya Rani, J. Ajayan, et al. · Journal of Circuits Systems and Computers
A novel high performance FinFET based multioutput hybrid carry skip-carry look ahead (CS-CLA) adder for future processors and cryptographic hardware
2026 · B Sandhya Rani, J Ajayan, et al. · Engineering Research Express
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Thermal dynamics of 7-nm FinFET process-based negative edge triggered (NET) TSPC D flip-flop for future AI and IoT applications
2025 · Syeda Hurmath Juveria, R. Shashank, et al. · Journal of the Korean Physical Society
Thermal Reliability Analysis for 7-nm FinFET Based Positive Edge Triggered TSPC Flip-Flop for Future IoT and AI Applications
2025 · Syeda Hurmath Juveria, J. Ajayan, et al. · Circuits Systems and Signal Processing
Thermal Dynamics of Aggressively Scaled Redundant Free Robust D Flip-Flop for Next Generation AI and IoT Applications
2025 · Syeda Hurmath Juveria, J. Ajayan, et al. · IEEE International Conference on Green Industrial Electronics and Sustainable Technologies (GIEST)
Thermal Reliability Study of Aggressively Scaled C2SFF for Future IoT Applications
2024 · Syeda Hurmath Juveria, Shashank Rebelli, et al. · International Conference on Smart Electronics and Communication Systems (ISENSE)
Investigation of Gate-Length Scaling Effects on the Thermal Reliability of 25T-TSPC Flip-Flop
2024 · Syeda Hurmath Juveria, Shashank Rebelli, et al. · International Conference on Smart Electronics and Communication Systems (ISENSE)
Works count: 8
Citation count: 2
H-index: 1
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