Concept

Boundary scan

OpenAlex ID: C992767

The Test Access Port and Boundary-Scan Architecture

1990 · C. Maunder, R. Tulloss · 804

Built-In Self-Test Techniques

1985 · Edward McCluskey · IEEE Design & Test of Computers · 420

Adapting scan architectures for low power operation

2002 · L. Whetsel · IEEE International Test Conference (ITC) · 267

IEEE Standard for Test Access Port and Boundary-Scan Architecture

2013 · 246

The Boundary — Scan Handbook

1992 · Kenneth P. Parker · Springer eBooks · 212

Scan chain design for test time reduction in core-based ICs

2002 · J. Aerts, E.J. Marinissen · IEEE International Test Conference (ITC) · 202

Securing Designs against Scan-Based Side-Channel Attacks

2007 · J. Lee, M. Tehranipoor, et al. · IEEE Transactions on Dependable and Secure Computing · 173

Design for Testability Using Scanpath Techniques for Path-delay Test and Measurement

2005 · B.I. Dervisoglu, G.E. Stong · IEEE International Test Conference (ITC) · 165

Testing and diagnosis of interconnects using boundary scan architecture

2003 · A. Hassan, J. Rajski, et al. · IEEE International Test Conference (ITC) · 143

A case study on the implementation of the Illinois Scan Architecture

2002 · F.F. Hsu, K.M. Butler, et al. · IEEE International Test Conference (ITC) · 128

Diagnosis of scan path failures

2002 · S. Edirisooriya, G. Edirisooriya · IEEE VLSI Test Symposium (VTS) · 110

VirtualScan: a new compressed scan technology for test cost reduction

2005 · L.-T. Wang, Xiaoqing Wen, et al. · IEEE International Test Conference (ITC) · 105

CMOS sensors for on-line thermal monitoring of VLSI circuits

1997 · V. Szekely, C. Marta, et al. · IEEE Transactions on Very Large Scale Integration (VLSI) Systems · 104

Built-In Self-Test Structures

1985 · Edward McCluskey · IEEE Design & Test of Computers · 101

Virtual scan chains: a means for reducing scan length in cores

2002 · A. Jas, B. Pouya, et al. · IEEE VLSI Test Symposium (VTS) · 95

Test data decompression for multiple scan designs with boundary scan

1998 · J. Rajski, J. Tyszer, et al. · IEEE Transactions on Computers · 94

Forensic imaging of embedded systems using JTAG (boundary-scan)

2006 · Ing. M.F. Breeuwsma · Digital Investigation · 93

Testing embedded cores using partial isolation rings

2002 · N.A. Touba, B. Pouya · IEEE VLSI Test Symposium (VTS) · 93

Reconfiguration technique for reducing test time and test data volume in Illinois Scan Architecture based designs

2003 · A.R. Pandey, J.H. Patel · IEEE VLSI Test Symposium (VTS) · 92

Diagnosis of scan chain failures

2002 · Yuejian Wu · Proceedings · 91

Survey of Scan Chain Diagnosis

2008 · Yu Huang, Ruifeng Guo, et al. · IEEE Design & Test of Computers · 89

Macro Testing: Unifying IC And Board Test

1986 · F.P.M. Beenker, K.j.e. Van Eerdewijk, et al. · IEEE Design & Test of Computers · 88

A unified theory for designing optimal test generation and diagnosis algorithms for board interconnects

2003 · C.W. Yau, N. Jarwala · IEEE International Test Conference (ITC) · 87

Multiscan-based test compression and hardware decompression using LZ77

2003 · F.G. Wolff, C. Papachristou · IEEE International Test Conference (ITC) · 84

Hybrid delay scan: a low hardware overhead scan-based delay test technique for high fault coverage and compact test sets

2004 · Seongmoon Wang, Liu Xiao, et al. · 82

Works count: 1,587

Citation count: 12,390