Work

IIIB-8 modeling physical limitations on junction scaling for CMOS

Year: 1983

Type: article

Source: IEEE Transactions on Electron Devices

DOI: 10.1109/t-ed.1983.21370

Authors: R.B. Fair, J.J. Wortman, J. Liu, M. Tischler, N.A. Masnari, K.Y. Duh

Institution: MCNC Research and Development Institute

Language: English

Topic: Advancements in Semiconductor Devices and Circuit Design

Subfield: Electrical and Electronic Engineering

Field: Engineering

Domain: Physical Sciences

Open Access status: closed

OpenAlex ID: W2027249820

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