Work

A 21.8–27.5GHz PLL in 32nm SOI using Gm linearization to achieve −130dBc/Hz phase noise at 10MHz offset from a 22GHz carrier

Year: 2012

Type: conference-paper

Source: Digest of papers - IEEE Radio Frequency Integrated Circuits Symposium

DOI: 10.1109/rfic.2012.6242235

Authors: Bodhisatwa Sadhu, Mark A. Ferriss, Jean-Olivier Plouchart, Arun S. Natarajan, Alexander V. Rylyakov, Alberto Valdes-Garcia, Benjamin D. Parker, Scott Reynolds, Aydin Babakhani, Soner Yaldiz, Larry Pileggi, Ramesh Harjani, Jose Tierno, Daniel Friedman

Institutions: University of Minnesota, IBM Research - Thomas J. Watson Research Center, Rice University, Carnegie Mellon University

Language: English

Topic: Advancements in PLL and VCO Technologies

Subfield: Electrical and Electronic Engineering

Field: Engineering

Domain: Physical Sciences

Open Access status: closed

OpenAlex ID: W2094254382

FWCI: 2.042

Cites: 10

Cited by: 9

Related to: 10