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José Tierno

Observed names: Jose A. Tierno, Jose Tierno, JosÉ A. Tierno, José A. Tierno, Tierno, Jose A., Tierno, José Andrés
OpenAlex ID: A5110197084
A 45nm CMOS neuromorphic chip with a scalable architecture for learning in networks of spiking neurons
2011 · Jae-sun Seo, Bernard Brezzo, et al. · Custom Integrated Circuits Conference · 344
A Wide Power Supply Range, Wide Tuning Range, All Static CMOS All Digital PLL in 65 nm SOI
2008 · JosÉ A. Tierno, Alexander V. Rylyakov, et al. · IEEE Journal of Solid-State Circuits · 194
Active management of timing guardband to save energy in POWER7
2011 · Charles R. Lefurgy, Alan J. Drake, et al. · IEEE/ACM International Symposium on Microarchitecture (MICRO) · 141
Introducing the Adaptive Energy Management Features of the Power7 Chip
2011 · Michael Floyd, Malcolm Allen-Ware, et al. · IEEE Micro · 117
A 19-Gb/s Serial Link Receiver With Both 4-Tap FFE and 5-Tap DFE Functions in 45-nm SOI CMOS
2012 · Ankur Agrawal, John F. Bulzacchelli, et al. · IEEE Journal of Solid-State Circuits · 79
A linearized, low-phase-noise VCO-based 25-GHz PLL with autonomic biasing
2013 · Bodhisatwa Sadhu, Mark A. Ferriss, et al. · IEEE Journal of Solid-State Circuits · 73
A cycle-accurate, cycle-reproducible multi-FPGA system for accelerating multi-core processor simulation
2012 · Sameh Asaad, Ralph Bellofatto, et al. · ACM/SIGDA International Symposium on Field-Programmable Gate Arrays (FPGA) · 73
Active Guardband Management in Power7+ to Save Energy and Maintain Reliability
2013 · Charles R. Lefurgy, Alan J. Drake, et al. · IEEE Micro · 64
An Integral Path Self-Calibration Scheme for a Dual-Loop PLL
2013 · Mark Ferriss, Jean-Olivier Plouchart, et al. · IEEE Journal of Solid-State Circuits · 54
A 28 GHz Hybrid PLL in 32 nm SOI CMOS
2014 · Mark Ferriss, Alexander Rylyakov, et al. · IEEE Journal of Solid-State Circuits · 52
A 1.4 pJ/bit, Power-Scalable 16×12 Gb/s Source-Synchronous I/O With DFE Receiver in 32 nm SOI CMOS Technology
2015 · Timothy O. Dickson, Yong Liu, et al. · IEEE Journal of Solid-State Circuits · 29
A DPLL-based per core variable frequency clock generator for an eight-core POWER7™ microprocessor
2010 · Jose Tierno, Alexander Rylyakov, et al. · Symposium on VLSI Circuits · 25
Indirect Performance Sensing for On-Chip Self-Healing of Analog and RF Circuits
2014 · Shupeng Sun, Fa Wang, et al. · IEEE Transactions on Circuits and Systems I Regular Papers · 24
A 19Gb/s serial link receiver with both 4-tap FFE and 5-tap DFE functions in 45nm SOI CMOS
2012 · Ankur Agrawal, John Bulzacchelli, et al. · Digest of technical papers/Digest of technical papers - IEEE International Solid-State Circuits Conference · 20
An Adaptively Pipelined Mixed Synchronous-Asynchronous Digital FIR Filter Chip Operating at 1.3 Gigahertz
2009 · Montek Singh, Jose A. Tierno, et al. · IEEE Transactions on Very Large Scale Integration (VLSI) Systems · 20
A wide tuning range (1 GHz-to-15 GHz) fractional-N all-digital PLL in 45nm SOI
2008 · Alexander Rylyakov, Jose Tierno, et al. · Custom Integrated Circuits Conference · 14
A 21.8–27.5GHz PLL in 32nm SOI using Gm linearization to achieve −130dBc/Hz phase noise at 10MHz offset from a 22GHz carrier
2012 · Bodhisatwa Sadhu, Mark A. Ferriss, et al. · Digest of papers - IEEE Radio Frequency Integrated Circuits Symposium · 9
An energy-complexity model for VLSI computations
1995 · José Tierno · 9
An integral path self-calibration scheme for a 20.1–26.7GHz dual-loop PLL in 32nm SOI CMOS
2012 · Mark Ferriss, Jean-Olivier Plouchart, et al. · Symposium on VLSI Circuits · 5
Designing Asynchronous Circuits in Gallium Arsenide
1993 · Tierno, Jose A. · CaltechAUTHORS (California Institute of Technology) · 3
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Correction to “A Linearized, Low Phase Noise VCO Based 25 GHz PLL With Autonomic Biasing”
2013 · Bodhisatwa Sadhu, Mark A. Ferriss, et al. · IEEE Journal of Solid-State Circuits · 1
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Self-healing analog/RF circuits
2016 · Shupeng Sun, Fa Wang, et al. · Institution of Engineering and Technology eBooks
A 1.4-pJ/b, power-scalable 16×12-Gb/s source-synchronous I/O with DFE receiver in 32nm SOI CMOS technology
2014 · Timothy O. Dickson, Yong Liu, et al. · Custom Integrated Circuits Conference
0.13∝m CMOS for Equalization of 10Gb/s Fiber-Optic Data Systems
2005 · Scott Reynolds, P. Pepeljugoski, et al.
An Asynchronous Microprocessor in Gallium Arsenide
1995 · José A. Tierno, Alain J. Martin, et al. · IFIP advances in information and communication technology
Works count: 31
Citation count: 1,350
H-index: 15
I10-index: 16
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