A 45nmLogicTechnology withHigh-k+Metal GateTransistors, Strained Silicon, 9CuInterconnect Layers, 193nmDryPatterning, and100%Pb-free Packaging
Year: 2007
Type: article
Authors: K. Mistry, C. C. Allen, C. Auth, Brian Beattie, D. Bergstrom, M. Bost, M. Brazier, Markus J. Buehler, A. Cappellani, R. Chau, Changhwan Choi, G. Ding, K. Fischer, T. Ghani, R. Grover, Weihua Han, Dennis G. Hanken, M. Hattendorf, J. Hicks, R. Huessner, D. Ingerly, Pulkit Jain, R. James, Lain‐Jong Li, Shalik Ram Joshi, C. Kenyon, Kelin J. Kuhn, Kyung Wook Lee, H. Liu, J. Maiz, B. McIntyre, Peter C. Moon, J. Neirynck, Sangwoo Pae, C. Parker, D. Parsons, C. Prasad, Leonard C. Pipes, M. B. Prince, P. Ranade, T.E. Reynolds, J. Sandford, L. Shifren, J. Sebastián, J. V. Seiple, Dan Simon, S. Sivakumar, P. Smith, Christopher W. Thomas, T. Troeger, P. Vandervoorn, Samuel Williams, K. Zawadzki
Language: English
Subfield: Electrical and Electronic Engineering
Field: Engineering
Domain: Physical Sciences
Open Access status: closed
OpenAlex ID: W2187359754