Work

Functional Obfuscation of Hardware Accelerators through Selective Partial Design Extraction onto an Embedded FPGA

Year: 2019

Type: conference-paper

Abstract: The protection of Intellectual Property (IP) has emerged as one of the most serious areas of concern in the semiconductor industry. To address this issue, we present a method and architecture to map selective portions of a design, given as a behavioral description for High-Level Synthesis (HLS) to a high-security embedded Field-Programmable Gate Array (eFPGA). In this manner, only the end-user has access to the full functionality of the chip. Using six benchmark circuits, we show that our approach is effective. In all cases, the Time-To-Break (TTB) is so long (at least 8 million hours) that for all practical purposes the designs are secure while incurring area overheads of around 5%. Further, latencies were only slightly increased, while the computation times are under one minute.

Source: ACM Great Lakes Symposium on VLSI (GLSVLSI)

DOI: 10.1145/3299874.3317992