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Carl Sechen
Observed names:
C. M. Sechen,
C. Sechen,
C.M. Sechen,
Carl M Sechen,
Carl M. Sechen,
Carl Matthew Sechen
show all 6
Institution:
The University of Texas at Dallas
Observed institutions:
The University of Texas at Dallas,
University of Washington,
Cirrus Logic (United States),
Yale University,
Massachusetts Institute of Technology,
Cadence Design Systems (United States),
University of California, Berkeley
show all 7
OpenAlex ID:
A5035758161
The TimberWolf placement and routing package
1985
·
C. Sechen
, A. Sangiovanni-Vincentelli
·
IEEE Journal of Solid-State Circuits
·
521
VLSI Placement and Global Routing Using Simulated Annealing
1988
·
Carl Sechen
·
Kluwer international series in engineering and computer science
·
228
Toward an Open-Source Digital Flow
2019
·
Tutu Ajayi
, Vidya A. Chhabria
, et al.
·
ACM/IEEE Design Automation Conference (DAC)
·
210
PDF
TimberWolf3.2
1986
·
Carl Sechen
, Alberto Sangiovanni-Vincentelli
·
ACM/IEEE Design Automation Conference (DAC)
·
191
PDF
Timing Driven Placement for Large Standard Cell Circuits
1995
·
William Swartz
, Carl Sechen
·
ACM/IEEE Design Automation Conference (DAC)
·
182
PDF
Efficient and effective placement for very large circuits
1995
·
Wern-Jieh Sun
, C. Sechen
·
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
·
117
New algorithms for the placement and routing of macro cells
2002
·
W. Swartz
, C. Sechen
·
International Conference on Computer Aided Design
·
103
A unified approach to the approximate symbolic analysis of large analog integrated circuits
1996
·
Qicheng Yu
, C. Sechen
·
IEEE Transactions on Circuits and Systems I Fundamental Theory and Applications
·
103
TimberWolf3.2: A New Standard Cell Placement and Global Routing Package
1986
·
C. Sechen
, A. Sangiovanni-Vincentelli
·
ACM/IEEE Design Automation Conference (DAC)
·
101
Chip-planning, placement, and global routing of macro/custom cell integrated circuits using simulated annealing
1988
·
Carl Sechen
·
86
A new global router for row-based layout
2003
·
K.-W. Lee
, C. Sechen
·
International Conference on Computer Aided Design
·
79
A MEMS-Assisted Temperature Sensor With 20- $\mu \text{K}$ Resolution, Conversion Rate of 200 S/s, and FOM of 0.04 pJK2
2016
·
Meisam Heidarpour Roshan
, Samira Zaliasl
, et al.
·
IEEE Journal of Solid-State Circuits
·
72
Gate sizing using Lagrangian relaxation combined with a fast gradient-based pre-processing step
2002
·
Hiran Tennakoon
, Carl Sechen
·
Digest of technical papers/Digest of technical papers - IEEE/ACM International Conference on Computer-Aided Design
·
69
Chip-planning, placement, and global routing of macro/custom cell integrated circuits using simulated annealing
2003
·
C. Sechen
·
ACM/IEEE Design Automation Conference (DAC)
·
61
Efficient and effective placement for very large circuits
2002
·
W.-J. Sun
, C. Sechen
·
International Conference on Computer Aided Design
·
53
DC small signal symbolic analysis of large analog integrated circuits
1994
·
Jer-Jaw Hsu
, C. Sechen
·
IEEE Transactions on Circuits and Systems I Fundamental Theory and Applications
·
53
An improved objective function for mincut circuit partitioning
2003
·
C. Sechen
, D. Chen
·
International Conference on Computer Aided Design
·
49
The charge-flow transistor: A new MOS device
1977
·
S. D. Senturia
, C. M. Sechen
, et al.
·
Applied Physics Letters
·
48
Clock-delayed domino for adder and combinational logic design
2002
·
Gin Yee
, C. Sechen
·
IEEE International Conference on Computer Design: VLSI in Computers and Processors (ICCD)
·
46
Timing and crosstalk driven area routing
1998
·
Hsiao-Ping Tseng
, L. Scheffer
, et al.
·
ACM/IEEE Design Automation Conference (DAC)
·
46
PDF
Clock-delayed domino for dynamic circuit design
2000
·
Gin Yee
, C. Sechen
·
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
·
44
Multiple FPGA Partitioning with Performance Optimization
1995
·
K. Roy-Neogi
, C. Sechen
·
ACM/SIGDA International Symposium on Field-Programmable Gate Arrays (FPGA)
·
41
PDF
Timing- and crosstalk-driven area routing
2001
·
Hsiao-Ping Tseng
, L. Scheffer
, et al.
·
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
·
40
Efficient canonical form for boolean matching of complex functions in large libraries
2003
·
J. Ciric
, C. Sechen
·
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
·
38
Design and synthesis of dynamic circuits
2003
·
T.J. Thorp
, G.S. Yee
, et al.
·
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
·
37
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Works count:
165
Citation count:
3,737
H-index:
32
I10-index:
67
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