Work

Clock-delayed domino for dynamic circuit design

Year: 2000

Type: article

Source: IEEE Transactions on Very Large Scale Integration (VLSI) Systems

DOI: 10.1109/92.863622

Authors: Gin Yee, C. Sechen

Institution: University of Washington

Language: English

Topic: Low-power high-performance VLSI design

Subfield: Electrical and Electronic Engineering

Field: Engineering

Domain: Physical Sciences

SDG: Industry, innovation and infrastructure

Open Access status: closed

OpenAlex ID: W2168753134

FWCI: 6.762

Cites: 14

Cited by: 44

Related to: 10