Work

Generating Test Patterns for Chiplet Interconnects With Optimized Effectiveness and Efficiency

Year: 2024

Type: article

Source: IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

DOI: 10.1109/tcad.2024.3466809

Authors: Po-Yao Chuang, Francesco Lorenzelli, Cheng-Wen Wu, Erik Jan Marinissen

Institutions: IMEC, National Tsing Hua University

Language: English

Topic: VLSI and Analog Circuit Testing

Subfield: Hardware and Architecture

Field: Computer Science

Domain: Physical Sciences

SDG: Industry, innovation and infrastructure

Open Access status: closed

OpenAlex ID: W4402742838

FWCI: 4.375

Cites: 28

Cited by: 14

Related to: 10