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Thermal-Aware Test Scheduling with Floor planning for Three-Dimensional Stacked Integrated Circuit

Year: 2024

Type: conference-paper

Source: IEEE International Conference on Semiconductor Electronics

DOI: 10.1109/icse62991.2024.10681395

Authors: Ganesan Patmanathan, Chia Yee Ooi, Nordinah Ismail, Siti Rahmah Aid

Institution: University of Technology Malaysia

Language: English

Topic: VLSI and Analog Circuit Testing

Subfield: Hardware and Architecture

Field: Computer Science

Domain: Physical Sciences

SDG: Industry, innovation and infrastructure

Open Access status: closed

OpenAlex ID: W4402836082

FWCI:

Cites: 15

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Related to: 10