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A Comprehensive Approach for Post Silicon Unique Hold Time Violation Debug on Ethernet Interface Issue

Year: 2024

Type: conference-paper

Source: Proceedings - International Symposium for Testing and Failure Analysis

DOI: 10.31399/asm.cp.istfa2024p0320

Authors: Lee Shen Shen, Kuan Lai Khei, Wu Jia Jun, Goh Lay Lay, Tirthak Shah, Gaurav Gupta, Vinay Padmanabha Gayatri, Yuet Li

Institution: Intel (United States)

Language: English

Topic: VLSI and Analog Circuit Testing

Subfield: Hardware and Architecture

Field: Computer Science

Domain: Physical Sciences

Open Access status: closed

OpenAlex ID: W4403685293

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