Work

Formal Verification of Nonlinear Analog Circuits using State Space-Based Model Order Reduction

Year: 2024

Type: conference-paper

Source: International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design

DOI: 10.1109/smacd61181.2024.10745444

Authors: Yasmine Abu-Haeyeh, Lars Hedrich

Institution: Goethe University Frankfurt

Language: English

Topic: Formal Methods in Verification

Subfield: Computational Theory and Mathematics

Field: Computer Science

Domain: Physical Sciences

Open Access status: closed

OpenAlex ID: W4404238762

FWCI: 1.157

Cites: 12

Cited by: 3

Related to: 10