Work

A System-Level Test Methodology for Communication Peripherals in System-on-Chips

Year: 2024

Type: article

Abstract: This paper deals with functional System-Level Test (SLT) for System-on-Chips (SoCs) communication peripherals. The proposed methodology is based on analyzing the potential weaknesses of applied structural tests such as Scan-based. Then, the paper illustrates how to develop a functional SLT programs software suite to address such issues. In case the communication peripheral provides detection/correction features, the methodology proposes the design of a hardware companion module to be added to the Automatic Test Equipment (ATE) to interact with the SoC communication module by purposely corrupting data frames. Experimental results are obtained on an industrial, automotive SoC produced by STMicroelectronics focusing on the Controller Area Network (CAN) communication peripheral and showing the effectiveness of the SLT suite to complement structural tests.

Source: IEEE Transactions on Computers

DOI: 10.1109/tc.2024.3500375

Authors: Francesco Angione, Paolo Bernardi, Nicola di Gruttola Giardino, Gabriele Filipponi, Claudia Bertani, Vincenzo Tancorre

Institutions: Politecnico di Torino, STMicroelectronics (Italy)

Language: English

Topic: VLSI and Analog Circuit Testing

Subfield: Hardware and Architecture

Field: Computer Science

Domain: Physical Sciences

SDG: Industry, innovation and infrastructure

Open Access status: hybrid

Estimated APC paid: $2,495