Work

An Efficient Method to Reduce Power in Built in Self Test

Year: 2024

Type: conference-paper

Source: IEEE Region 10 Symposium (TENSYMP)

DOI: 10.1109/tensymp61132.2024.10752235

Authors: Sidharth S, Ramesh S R

Institution: Amrita Vishwa Vidyapeetham

Language: English

Topic: VLSI and Analog Circuit Testing

Subfield: Hardware and Architecture

Field: Computer Science

Domain: Physical Sciences

SDG: Industry, innovation and infrastructure

Open Access status: closed

OpenAlex ID: W4404521060

FWCI: 0.621

Cites: 16

Cited by: 2

Related to: 10