Year: 2024
Type: article
Abstract: Testing memory circuits is crucial for ensuring the quality and reliability of system-on-chip (SoC) designs, especially as shrinking technology nodes increase susceptibility to nanometer-scale defects. This article introduces an enhanced methodology for memory testing, leveraging the cell-aware (CA) test concept. Building on prior work for SRAM array testing (Xhafa et al., 2023), we extend the CA methodology to include periphery testing by generating, for the first time, CA models for each memory input–output (I/O) element, covering key components, such as address decoders, write drivers, and sense amplifiers. We present results from testing these periphery components using the CA methodology. Additionally, we compare existing SRAM testing techniques with our CA methodology for the decoder and I/O circuitry. To ensure a fair comparison, we selected minimal March tests designed to detect functional faults in peripheral circuits, aligning with the fault models targeted by our approach. A quantitative analysis of fault coverage demonstrates the effectiveness of our methodology compared to March algorithms, particularly in terms of test complexity.
Language: English
Subfield: Hardware and Architecture
Field: Computer Science
Domain: Physical Sciences
Open Access status: green
Award: G1185244426
OpenAlex ID: W4404739939