A 3 nm-FinFET 4.3 GHz 21.1 Mb/mm 2 Double-Pumping 1-Read and 1-Write Psuedo-2-Port SRAM With a Folded Bitline Multi-Bank Architecture
Year: 2024
Type: article
Authors: Masaru Haraguchi, Yorinobu Fujino, Yoshisato Yokoyama, Ming-Hung Chang, Yu-Hao Hsu, Hong-Chen Cheng, Koji Nii, Yih Wang, Tsung-Yung Jonathan Chang
Institution: Taiwan Semiconductor Manufacturing Company (Taiwan)
Language: English
Subfield: Electrical and Electronic Engineering
Field: Engineering
Domain: Physical Sciences
Open Access status: closed
OpenAlex ID: W4405304047