Work

Robust and Efficient Implementation of Design for Testability in Integrated Circuits

Year: 2024

Type: conference-paper

DOI: 10.1109/csitss64042.2024.10816981

Authors: Skanda V Jois, Ravish Aradhya H V

Institution: R.V. College of Engineering

Language: English

Topic: VLSI and Analog Circuit Testing

Subfield: Hardware and Architecture

Field: Computer Science

Domain: Physical Sciences

SDG: Industry, innovation and infrastructure

Open Access status: closed

OpenAlex ID: W4405974609

FWCI: 0.322

Cites: 15

Cited by: 1

Related to: 10