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Cell-Aware ATPG under Electrical Voltage Stress

Year: 2024

Type: conference-paper

DOI: 10.1109/wintechcon61988.2024.10837789

Authors: Shruthi Shekarappa, Nand Kishore, Sahil Narang, Aenikapati Swetha Priya, Navdeep Sood, Sameer Chillarige

Institution: Cadence Design Systems (India)

Language: English

Topic: VLSI and Analog Circuit Testing

Subfield: Hardware and Architecture

Field: Computer Science

Domain: Physical Sciences

SDG: Industry, innovation and infrastructure

Open Access status: closed

OpenAlex ID: W4406354953

FWCI:

Cites: 23

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Related to: 10