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Improving At-Speed Test Coverage without compromising Test Time and reducing Test Cost in multi-partition SCAN Design

Year: 2024

Type: conference-paper

Source: Proceedings - Asian Test Symposium/Proceedings

DOI: 10.1109/ats64447.2024.10915249

Authors: Jayesh Popat, Ramesh Devani, Jay Gohil

Language: English

Topic: VLSI and Analog Circuit Testing

Subfield: Hardware and Architecture

Field: Computer Science

Domain: Physical Sciences

SDG: Industry, innovation and infrastructure

Open Access status: closed

OpenAlex ID: W4408443155

FWCI: 0.322

Cites: 7

Cited by: 1

Related to: 10