Work

Fault Simulation Algorithm for Transistor Stuck Fault in VLSI Testing

Year: 2025

Type: conference-paper

Source: Devices for Integrated Circuit (DevIC)

DOI: 10.1109/devic63749.2025.11012179

Authors: Madhu Naik Nenavath, Sobhit Saxena, Suman Lata Tripathi

Institutions: Lovely Professional University, Symbiosis International University

Language: English

Topic: VLSI and Analog Circuit Testing

Subfield: Hardware and Architecture

Field: Computer Science

Domain: Physical Sciences

Open Access status: closed

OpenAlex ID: W4410853322

FWCI: 1.856

Cites: 9

Cited by: 2

Related to: 10