Work

A New Test Point Insertion Using Weight Adjusted Grouping

Year: 2025

Type: article

Abstract: Integrated circuits (ICs) require high test coverage to ensure reliability and performance even during operation, which can be challenging with standard testing methods. Logic built-in self-test (BIST) is introduced to address the issue. Since Logic BIST generates patterns through a pseudo random pattern generator (PRPG), it requires lots of test patterns, resulting in a long test time to achieve the target coverage. To address this drawback, test point insertion (TPI) is employed as a potential solution. While TPI enables to increase test coverage efficiently by directly targeting locations with low testability, it inevitably incurs area overhead due to the additional logic and wires. To address these limitations, a new weight adjusted grouping based efficient test point insertion method (WAG) is proposed in this paper to achieve high test coverage with less test time and area overhead. Weight adjustment flip-flops (WAFFs) and the following load flip-flops (LOFFs) are selected based on specified-bit ratio and weight. WAG biases the outputs of the flip-flops and inserts control points by adding only a few gates to the selected WAFFs and LOFFs. Experimental results on ITC’99 and industrial circuits demonstrate this approach. This paper is notable for its effectiveness in reducing test time while improving test coverage and minimizing area overhead.

Source: IEEE Access

DOI: 10.1109/access.2025.3575800

Authors: Jaehyun Kim, Hyemin Kim, Jongho Park, Sangjun Lee, Sungho Kang

Institutions: Yonsei University, Samsung (South Korea), Samsung Electronics (South Korea)

Language: English

Topic: VLSI and Analog Circuit Testing

Subfield: Hardware and Architecture

Field: Computer Science

Domain: Physical Sciences

SDG: Industry, innovation and infrastructure

Open Access status: gold

Estimated APC paid: $2,075