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Architecting Test-Friendly Multi-Mode Scan Flip-Flops for Modern Low-Power Digital Systems

Year: 2025

Type: conference-paper

DOI: 10.1109/ictest64710.2025.11042550

Authors: T. R. Dinesh Kumar, S. SivaSaravana Babu, M. Parthiban, Hemanth. S, Infant. T, Jayan. G, Deepa Dharsan. B.S

Institution: Vel Tech Rangarajan Dr. Sagunthala R&D Institute of Science and Technology

Language: English

Topic: VLSI and Analog Circuit Testing

Subfield: Hardware and Architecture

Field: Computer Science

Domain: Physical Sciences

SDG: Industry, innovation and infrastructure

Open Access status: closed

OpenAlex ID: W4411584405

FWCI: 0.928

Cites: 15

Cited by: 1

Related to: 10