Work

A 65nm 100MS/s-400MS/s Multi-Column SAR/SS ADC with Reconfigurable 2-8 Bit Resolution for Optical and In-memory Computing

Year: 2025

Type: conference-paper

Source: IEEE International Symposium on Circuits and Systems proceedings

DOI: 10.1109/iscas56072.2025.11043337

Authors: Anying Jiang, Ye Lin, Jiayuan Chen, Wenhe Yin, Yize Wang, Mingqian Yang, Li Du, Yuan Du

Institutions: Nanjing University, China Mobile Research Institute, Beijing Microelectronics Technology Institute

Language: English

Topic: Analog and Mixed-Signal Circuit Design

Subfield: Biomedical Engineering

Field: Engineering

Domain: Physical Sciences

Open Access status: closed

Funder: Research and Development

OpenAlex ID: W4411725678

FWCI: 2.903

Cites: 9

Cited by: 1

Related to: 10