Work

Cost-Effective High-Speed DRAM Testing: Circuit-Level Enhancements with Clock Multiplication and ECC

Year: 2025

Type: conference-paper

Source: International Conference on IC Design and Technology

DOI: 10.1109/icicdt65192.2025.11078066

Authors: Kyungjun Lee, Juyeob Lee, Eunil Park

Institutions: Samsung Electronics (South Korea), Sungkyunkwan University

Language: English

Topic: VLSI and Analog Circuit Testing

Subfield: Hardware and Architecture

Field: Computer Science

Domain: Physical Sciences

Open Access status: closed

OpenAlex ID: W4413067422

FWCI:

Cites: 14

Cited by:

Related to: 10