Year: 2025
Type: article
Abstract: The Memory Built-In Self-Test (MBIST) is the standard for testing dense embedded memories that dominate modern SoCs; however, a critical trade-off exists between the test time and fault coverage. While comprehensive algorithms such as March C- (10n) are slow, faster algorithms such as MATS++ (6n) are often preferred, although both aim to detect critical Address Decoder Faults (AFs). This study presents an MBIST controller employing a novel March (5n) algorithm that bridges this gap, offering robust fault coverage with superior efficiency. The core innovation of the algorithm is the "address-as-data" paradigm, which uses the memory address (a) and its bitwise complement (~a) as test patterns to efficiently detect Stuck-at (SAF), Transition (TF), and Address Decoder (AF) faults. The proposed FSM-based controller has been designed in Verilog and validated on a Xilinx Zynq-7000 series FPGA platform. Experimental evaluation demonstrates that the March (5n) algorithm achieves significant reductions in test time compared to established approaches, with minimal resource overhead. These findings highlight the effectiveness of the March (5n) algorithm in achieving a balanced trade-off between speed and fault coverage, positioning it as a practical candidate for deployment in high-volume, cost-sensitive applications.
Authors: Ahmed Salahuddin Suhaib, M. Asha Rani
Institution: Jawaharlal Nehru Technological University, Hyderabad
Language: English
Subfield: Hardware and Architecture
Field: Computer Science
Domain: Physical Sciences
Open Access status: gold
OpenAlex ID: W4414004903