Year: 2025
Type: conference-paper
Abstract: Printed Electronics (PE) has emerged as a superior alternative to traditional silicon-based technologies for applications requiring mechanical, flexibility, point-of-use customization, low-cost fabrication, and energy efficiency. PE is particularly wellsuited for low-power edge devices, such as wearable healthcare systems, environmental monitoring patches, and flexible diagnostic tools, where lightweight, adaptable, and efficient solutions are essential. Leveraging PE, printed analog neuromorphic circuits (pNCs) enable energy-efficient neural computations, making them ideal for classification tasks in target applications. However, the additive manufacturing processes inherent to PE increase susceptibility to defects, posing significant challenges for reliable operation and necessitating robust fault detection mechanisms. To address this, we propose a novel Automatic Test Pattern Generation (ATPG) framework tailored for pNCs, integrating fault abstraction and gradient-based test input generation. Fault modeling and abstraction reduces the fault space by clustering faults with similar transfer functions and removing untestable faults, thereby enhancing testing efficiency. In our experiments, the fault space was reduced by a factor of 2.28. The proposed framework refines test inputs through gradient-based optimization, maximizing output discrepancies between fault-free and faulty circuits. We evaluate the method on nine trained models across multiple datasets, achieving fault coverage exceeding 90% with fewer test vectors compared to random search.
Authors: Gheshlaghi, Tara, Pal, Priyanjana, Studt, Alexander, Hefenbrock, Michael, Beigl, Michael, Tahoori, Mehdi B.
Language: English
Subfield: Hardware and Architecture
Field: Computer Science
Domain: Physical Sciences
Open Access status: green
OpenAlex ID: W6894199315
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