Corrections to “Enhancing Memory BIST With an Optimized RTL-BIST IP Core: A Low-Power, High-Fault-Coverage Approach”
Year: 2025
Type: erratum
Authors: Ming-Yi Lin, Wei-Kuan Chiang, Chin-Hung Wang
Institution: Yuan Ze University
Language: English
Subfield: Hardware and Architecture
Field: Computer Science
Domain: Physical Sciences
Open Access status: closed
OpenAlex ID: W7083422167