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K.: Multiple Scan Chain Design Technique for Power Reduction during Test Application

Type: article

Authors: Debjyoti Ghosh, Swarup Bhunia, Kaushik Roy

Language: English

Topic: VLSI and Analog Circuit Testing

Subfield: Hardware and Architecture

Field: Computer Science

Domain: Physical Sciences

SDG: Industry, innovation and infrastructure

Open Access status: closed

OpenAlex ID: W7096739468

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Related to: 10