Reducing Test Response Volume and Test Time in Direct-Access-Based High-Bandwidth Memory Testing
Year: 2026
Type: article
Abstract: In high-bandwidth memory (HBM) testing through the direct access (DA) port, the response-path bandwidth is far lower than the internal data bandwidth. Because most read responses are fault-free, transferring every response incurs substantial transfer overhead and test time. This paper proposes three fault-data transfer methods. Selective staggered read suppresses fault-free response transfers and overlaps faulty-response transfers with the subsequent read latency. Duplicate fault suppression replaces identical fault responses at consecutive addresses with a short duplicate code. Failing-bit indexing transmits only the positions of failing bits. The proposed architecture controls whether, when, and in which format each response is transferred without modifying the DA port interface or the March command and address sequence. Cycle-accurate simulation of an HBM2 test model shows that, across Random, Column-Correlated, and Row-Correlated Fault models with fault rates of 0.01–5%, the proposed method reduces the DA response data by 99.32–99.99% and the total test time by 44.86–45.01% compared with the conventional method. Synthesis shows that the added logic is smaller than that of on-chip fault collection and signature compaction schemes and independent of the memory capacity. The proposed architecture attains nearly the same test time as on-chip fault collection and signature compaction schemes while delivering every faulty response and its failing-bit positions to the tester, so that its diagnostic coverage is not bounded by on-chip storage.
Source: Electronics
Institution: Hoseo University
Language: English
Subfield: Hardware and Architecture
Field: Computer Science
Domain: Physical Sciences
Open Access status: gold
Estimated APC paid: $2,896
OpenAlex ID: W7225180152