Author

P. Cavalloro

Observed names: Cavalloro, Patrizia, Patrizia Cavalloro

Observed institution: Italtel (Italy)

OpenAlex ID: A5000272580

ALADIN: a multilevel testability analyzer for VLSI system design

1994 · M. Bombana, G. Buonanno, et al. · IEEE Transactions on Very Large Scale Integration (VLSI) Systems · 19

INCA: an expert system for process planning in PCB assembly line

2003 · P. Cavalloro, E. Cividati · IEEE Conference on Artificial Intelligence Applications (CAIA) · 13

A multilevel testability assistant for VLSI design

2003 · M. Bombana, G. Buonanno, et al. · European Design Automation Conference (EURO-DAC) · 10

A wafer level testability approach based on an improved scan insertion technique

1995 · C. Bolchini, G. Buonanno, et al. · IEEE Transactions on Components Packaging and Manufacturing Technology Part B · 8

ATM cell modelling using objective VHDL

2002 · A. Allara, M. Bombana, et al. · Asia and South Pacific Design Automation Conference (ASP-DAC) · 6

System Level Design Model with Reuse of System IP

2003 · Cavalloro, Patrizia, Voros, Nikolaos S, et al. · Springer eBooks · 5

Design-Flow and Synthesis for ASICs: A Case Study

1995 · Massimo Bombana, Patrizia Cavalloro, et al. · ACM/IEEE Design Automation Conference (DAC) · 4

A design methodology for the correct specification of VLSI systems

1993 · C. Bolchini, M. Bombana, et al. · Microprocessing and Microprogramming · 4

Specification and formal synthesis of digital circuits

1993 · M. Bombana, P. Cavalloro, et al. · Elsevier eBooks · 4

Cycles analysis for testability of WSI sequential architectures

2002 · M. Bombana, G. Buonanno, et al. · International Conference on Wafer Scale Integration (ICWSI) · 3

CASTOR: an expert advisor for testability enhancement of VLSI systems

2002 · G. Bezzi, C. Bolchini, et al. · Conference on Artificial Intelligence for Applications · 3

Quantitative evaluation of formal based synthesis in ASIC design

1995 · G. Bezzi, M. Bombana, et al. · Lecture notes in computer science · 3

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Reduction of fault detection costs through testable design of sequential architectures with signal feedbacks

2002 · M. Bombana, G. Buonanno, et al. · Proceedings · 1

Property verification in the design of telecom applications

2002 · M. Bombana, P. Cavalloro, et al. · Asia and South Pacific Design Automation Conference (ASP-DAC) · 1

C/C ++: progress or deadlock in system-level specification

2005 · E. Villar, D. Gajski, et al. · Design, Automation, and Test in Europe

Concepts for System Specification and Design Languages

2004 · Patrizia Cavalloro · Springer eBooks

Towards WSI testable devices: an improved scan insertion technique

2002 · C. Bolchini, G. Buonanno, et al. · International Conference on Wafer Scale Integration (ICWSI)

Italtel Application of the FORMAT Design Flow

1997 · Massimo Bombana, Patrizia Cavalloro, et al. · Springer eBooks

An Expert Solution to Functional Testability Analysis of VLSI Circuits.

1993 · M. Bombana, G. Buonanno, et al. · Proceedings/Proceedings of the ... International Conference on Software Engineering and Knowledge Engineering

The Patricia testability analysis tool

1991 · M. Hadjinicolaeu, N. Burgess, et al. · Microprocessing and Microprogramming

Works count: 26

Citation count: 84

H-index: 5

I10-index: 3