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Robert L. Hsieh

Observed names: Hsieh Robert, R. L. HSIEH, R. L. Hsieh, R.L. Hsieh, Robert Hsieh
OpenAlex ID: A5000796590
One Micron Damascene Redistribution for Fan-Out Wafer Level Packaging using a Photosensitive Dielectric Material
2018 · Warren W. Flack, Robert Hsieh, et al. · IEEE Electronics Packaging Technology Conference (EPTC) · 21
One micron redistribution for fan-out wafer level packaging
2017 · Warren W. Flack, Robert Hsieh, et al. · IEEE Electronics Packaging Technology Conference (EPTC) · 18
1/8 μm optical lithography
1992 · G. Owen, R. F. W. Pease, et al. · Journal of Vacuum Science & Technology B Microelectronics and Nanometer Structures Processing Measurement and Phenomena · 14
Large area interposer lithography
2014 · Warren Flack, Robert Hsieh, et al. · IEEE Electronic Components and Technology Conference (ECTC) · 13
Fine Pitch Line/Space Lithography for Large Area Package with Multi-Field Stitching
2021 · Soon Wee Ho, Norman Yen, et al. · IEEE Electronic Components and Technology Conference (ECTC) · 9
Effect of central obscuration on image formation in projection lithography
1990 · Steven T. Yang, Robert L. Hsieh, et al. · Proceedings of SPIE, the International Society for Optical Engineering/Proceedings of SPIE · 9
Markle–Dyson optics for 0.25 μm lithography and beyond
1991 · A. Grenville, R. L. Hsieh, et al. · Journal of Vacuum Science & Technology B Microelectronics and Nanometer Structures Processing Measurement and Phenomena · 7
Process Window Enhancement of Via Holes for Fine Pitch RDL by Design Optimization
2020 · Cliff McCold, Robert Hsieh, et al. · IEEE Electronic Components and Technology Conference (ECTC) · 6
Dual side lithography measurement, precision, and accuracy
2005 · Daniel Schurz, Warren W. Flack, et al. · Proceedings of SPIE, the International Society for Optical Engineering/Proceedings of SPIE · 5
Lithography technique to reduce the alignment errors from die placement in fan-out wafer level packaging applications
2011 · Warren Flack, Robert Hsieh, et al. · IEEE Electronic Components and Technology Conference (ECTC) · 3
Development and characterization of a 300-mm dual-side alignment stepper
2007 · Warren W. Flack, Emily M. True, et al. · Proceedings of SPIE, the International Society for Optical Engineering/Proceedings of SPIE · 3
Rational argument for the impracticability of 1× reticles
1993 · Gerry Owen, Roger Fabian W. Pease, et al. · Proceedings of SPIE, the International Society for Optical Engineering/Proceedings of SPIE · 2
All-reflective phase-shifting masks for Markle–Dyson optics
1992 · Robert L. Hsieh, Andrew Grenville, et al. · Journal of Vacuum Science & Technology B Microelectronics and Nanometer Structures Processing Measurement and Phenomena · 2
Reflective masks for 1X deep ultraviolet lithography
1992 · Robert L. Hsieh, Julienne Y. Lee, et al. · Proceedings of SPIE, the International Society for Optical Engineering/Proceedings of SPIE · 1
Silicon on quartz reflective masks for 0.25-μm microlithography
1991 · Y. H. Lee, R. L. Hsieh, et al. · Journal of Vacuum Science & Technology B Microelectronics and Nanometer Structures Processing Measurement and Phenomena · 1
Cation Valence in VO x
1984 · Robert L. Hsieh, Jerome B. Cohen, et al. · Journal of the American Ceramic Society · 1
Enabling Fan-Out Wafer-Level Package (FOWLP) through Innovative Lithography and Electrodeposition Technology
2017 · Justin Oberst, Bryan Buckalew, et al. · Wafer-Level Packaging Symposium
Overlay performance of through Si via last lithography for 3D packaging
2016 · Warren W. Flack, Robert Hsieh, et al. · IEEE Electronics Packaging Technology Conference (EPTC)
3次元パッケージングのための最終リソグラフィーによるSiのオーバレイ性能【Powered by NICT】
2016 · W Flack Warren, Hsieh Robert, et al. · IEEE Conference Proceedings
Optimization of Through Si Via Last Lithography for 3D Packaging
2015 · Warren W. Flack, Robert Hsieh, et al. · Wafer-Level Packaging Symposium
Bosch Process Characterization for Donut TSV’S
2014 · John Slabbekoorn, Bart Schepers, et al. · Wafer-Level Packaging Symposium
Microbump Lithography for 3D Stacking Applications
2013 · Patrick Jaenen, John Slabbekoorn, et al. · Wafer-Level Packaging Symposium
Verification of Back-to-Front Side Alignment for Advanced Packaging
2012 · Warren W. Flack, Manish Ranjan, et al. · Wafer-Level Packaging Symposium
Lithography Challenges for Leading Edge 3D Packaging Applications
2011 · Warren W. Flack, Manish Ranjan, et al. · Wafer-Level Packaging Symposium
Lithography Challenges and Considerations for Emerging Fan-Out Wafer Level Packaging Applications
2009 · Robert L. Hsieh, Detlef Fuchs, et al. · Wafer-Level Packaging Symposium
Works count: 31
Citation count: 115
H-index: 7
I10-index: 4
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