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Veezhinathan Kamakoti

Observed names: Kamakoti V, Kamakoti V., Kamakoti v, Kamakoti, V, V Kamakoti, V Kamakoti., V. Kamakoti
Observed institutions: California Institute of Technology, National Institute of Technology Tiruchirappalli, Indian Institute of Technology Madras, Texas Instruments (India), Indian Institute of Science Bangalore, Institute of Mathematical Sciences, Colorado State University
ORCID: 0000-0003-2332-8538
Observed ORCID: 0000-0003-2332-8538
OpenAlex ID: A5010004459
Attention guided grad-CAM : an improved explainable artificial intelligence model for infrared breast cancer detection
2023 · Kaushik Raghavan, Sivaselvan B, et al. · Multimedia Tools and Applications · 105
Efficient Building Blocks for Reversible Sequential Circuit Design
2006 · Siva Kumar Sastry Hari, Shyam Shroff, et al. · IEEE International Midwest Symposium on Circuits and Systems (MWSCAS) · 77
SHAKTI Processors: An Open-Source Hardware Initiative
2016 · Neel Gala, Arjun Menon, et al. · International Conference on VLSI Design · 61
PERI
2021 · Sugandha Tiwari, Neel Gala, et al. · ACM Transactions on Architecture and Code Optimization · 53
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A bus encoding technique for power and cross-talk minimization
2004 · P. Subrahmanya, R. Manimegalai, et al. · International Conference on VLSI Design · 50
Karna: A Gate-Sizing based Security Aware EDA Flow for Improved Power Side-Channel Attack Protection
2019 · Patanjali Slpsk, Prasanna Karthik Vairam, et al. · 43
SHAKTI-F: A Fault Tolerant Microprocessor Architecture
2015 · Sukrat Gupta, Neel Gala, et al. · Proceedings - Asian Test Symposium/Proceedings · 43
PROLEMus: A Proactive Learning-Based MAC Protocol Against PUEA and SSDF Attacks in Energy Constrained Cognitive Radio Networks
2019 · Milan Patnaik, V. Kamakoti, et al. · IEEE Transactions on Cognitive Communications and Networking · 42
Glitch-Aware Pattern Generation and Optimization Framework for Power-Safe Scan Test
2007 · V.R. Devanathan, C.P. Ravikumar, et al. · IEEE VLSI Test Symposium (VTS) · 38
Dynamic coding technique for low-power data bus
2003 · M. Madhu, V.S. Murty, et al. · IEEE Computer Society Annual Symposium on VLSI · 30
Ultra folded high-speed architectures for Reed Solomon decoders
2006 · K. Seth, K.N. Viswajith, et al. · International Conference on VLSI Design · 28
A stochastic pattern generation and optimization framework for variation-tolerant, power-safe scan test
2007 · V.R. Devanathan, C.P. Ravikumar, et al. · IEEE International Test Conference (ITC) · 27
On Power-profiling and Pattern Generation for Power-safe Scan Tests
2007 · V.R. Devanathan, C.P. Ravikumar, et al. · Design, Automation, and Test in Europe · 26
System-on-programmable-chip implementation for on-line face recognition
2006 · A. Pavan Kumar, V. Kamakoti, et al. · Pattern Recognition Letters · 26
Detecting SEU-caused routing errors in SRAM-based FPGAs
2005 · E.S.S. Reddy, V. Chandrasekhar, et al. · International Conference on VLSI Design · 26
The implications of shared data synchronization techniques on multi-core energy efficiency
2012 · Ashok Gautham, Kunal Korgaonkar, et al. · International Conference on Power aware computing and systems · 24
Power Virus Generation Using Behavioral Models of Circuits
2007 · K. Najeeb, Vishnu Vardhan Reddy Konda, et al. · IEEE VLSI Test Symposium (VTS) · 23
PMScan : A power-managed scan for simultaneous reduction of dynamic and leakage power during scan test
2007 · V.R. Devanathan, C.P. Ravikumar, et al. · IEEE International Test Conference (ITC) · 22
ProMAC: A proactive model predictive control based MAC protocol for cognitive radio vehicular networks
2016 · N. Sathya Narayanan, Milan Patnaik, et al. · Computer Communications · 19
A novel CLB architecture to detect and correct SEU in LUTs of SRAM-based FPGAs
2005 · E.S. Sundar, V. Chandrasekhar, et al. · International Conference on Field-Programmable Technology (FPT) · 19
RaDaR: A Real-Word Dataset for AI powered Run-time Detection of Cyber-Attacks
2022 · Sareena Karapoola, Nikhilesh Singh, et al. · ACM International Conference on Information and Knowledge Management (CIKM) · 16
Efficient Motion Vector Recovery Algorithm for H.264 Using B-Spline Approximation
2010 · Kavish Seth, V. Kamakoti, et al. · IEEE Transactions on Broadcasting · 15
Automatic Constraint Based Test Generation for Behavioral HDL Models
2008 · Siva Kumar Sastry Hari, Vishnu Vardhan Reddy Konda, et al. · IEEE Transactions on Very Large Scale Integration (VLSI) Systems · 14
A universal random test generator for functional verification of microprocessors and system-on-chip
2005 · K. Uday Bhaskar, M. Prasanth, et al. · International Conference on VLSI Design · 14
Placement and routing for 3D-FPGAs using reinforcement learning and support vector machines
2005 · R. Manimegalai, E. Siva Soumya, et al. · International Conference on VLSI Design · 14
Works count: 153
Citation count: 1,255
H-index: 19
I10-index: 33
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