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Shinobu Okanishi

Observed name: S. Okanishi
Observed institution: Renesas Electronics (Japan)
OpenAlex ID: A5011908722
A Perpetuum Mobile 32bit CPU with 13.4pJ/cycle, 0.14µA sleep current using Reverse Body Bias Assisted 65nm SOTB CMOS technology
2014 · Koichiro Ishibashi, Nobuyuki Sugii, et al. · IEEE Symposium in Low-Power and High-Speed Chips (COOL CHIPS) · 22
Ultralow-voltage design and technology of silicon-on-thin-buried-oxide (SOTB) CMOS for highly energy efficient electronics in IoT era
2014 · Shiro Kamohara, Nobuyuki Sugii, et al. · Symposium on VLSI Technology · 12
Reliability and scalability of FinFET split-gate MONOS array with tight Vth distribution for 16/14nm-node embedded flash
2017 · S. Tsuda, T. Saito, et al. · Technical digest - International Electron Devices Meeting/Technical digest · 9
A Silicon-on-Thin-Buried-Oxide CMOS Microcontroller with Embedded Atom-Switch ROM
2015 · Toshitsugu Sakamoto, Yukihide Tsuji, et al. · IEEE Micro · 6
Low-power embedded read-only memory using atom switch and silicon-on-thin-buried-oxide transistor
2015 · Toshitsugu Sakamoto, Munehiro Tada, et al. · Applied Physics Express · 5
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Realization of “skeleton wafer” testing for electrical failure analysis
2018 · Hiroshi Yanagita, Akihito Jingu, et al. · IEEE International Symposium on Semiconductor Manufacturing conference proceedings · 2
Comprehensive analysis of low-frequency noise variability components in bulk and fully depleted silicon-on-insulator metal–oxide–semiconductor field-effect transistor
2018 · Keiichi Maekawa, Hideki Makiyama, et al. · Japanese Journal of Applied Physics · 2
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0.39-V, 18.26-µW/MHz SOTB CMOS Microcontroller with embedded atom switch ROM
2015 · Toshitsugu Sakamoto, Yukihide Tsuji, et al. · IEEE Symposium in Low-Power and High-Speed Chips (COOL CHIPS) · 2
Cost-Effective and Time-Efficient Failure Analysis Method for Yield Enhancement Utilizing Picked Sawn Wafer
2019 · Hiroshi Yanagita, Akihito Jingu, et al. · IEEE Transactions on Semiconductor Manufacturing · 1
招待講演 : A Perpetuum Mobile 32bit CPU with 13.4pJ/cycle, 0.14μA Sleep Current using Reverse-Body-Bias Assisted 65nm SOTB CMOS Technology (シリコン材料・デバイス)
2014 · Koichiro Ishibashi, Nobuyuki Sugii, et al. · IEICE technical report. Speech · 1
Material-Dependent SDL Behavior of Cu-Void Defects: An Integrated Electrical and Physical Failure Analysis
2026 · Toru Takahashi, Akiko Hisasue, et al. · Proceedings - International Symposium for Testing and Failure Analysis
Reliability and Scalability of FinFET Split-Gate MONOS Array with Tight Vth Distribution for 16/14nm-node Embedded Flash
2018 · Shibun Tsuda, Tomoya Saito, et al. · IEICE Technical Report; IEICE Tech. Rep.
Time-dependent Vth shift of silicon on thin BOX under large back bias
2017 · Yoshiki Yamamoto, Hideki Makiyama, et al. · IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference
Comprehensive Analysis of Low-frequency Noise Variability Components in Bulk and FDSOI (SOTB) MOSFETs
2017 · K. Maekawa, H. Makiyama, et al. · International Conference on Solid State Devices and Materials (SSDM)
Back-Bias Control Technique for Suppression of Die-to-Die Delay Variability of SOTB MOS Circuits at Ultralow-Voltage (0.4 V) Operation
2014 · Hideki Makiyama, Y. Yamamoto, et al. · Technical report of IEICE. SDM
Works count: 15
Citation count: 62
H-index: 5
I10-index: 2
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