Work

Cost-Effective and Time-Efficient Failure Analysis Method for Yield Enhancement Utilizing Picked Sawn Wafer

Year: 2019

Type: article

Source: IEEE Transactions on Semiconductor Manufacturing

DOI: 10.1109/tsm.2019.2934115

Authors: Hiroshi Yanagita, Akihito Jingu, Shinobu Okanishi, Satoshi Tanaka, Toru Koyama

Institution: Renesas Electronics (Japan)

Language: English

Topic: Integrated Circuits and Semiconductor Failure Analysis

Subfield: Electrical and Electronic Engineering

Field: Engineering

Domain: Physical Sciences

Open Access status: closed

Funder: RIKEN

OpenAlex ID: W2968060056

FWCI: 0.09

Cites: 6

Cited by: 1

Related to: 10