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Nam-Jong Kim

A 2.5-V, 333-Mb/s/pin, 1-Gbit, double-data-rate synchronous DRAM
1999 · Hongil Yoon, Gi-Won Cha, et al. · IEEE Journal of Solid-State Circuits · 24
A Duo-Binary Transceiver With Time-Based Receiver and Voltage-Mode Time-Interleaved Mixing Transmitter for DRAM Interface
2021 · Min-Kyun Chae, Hye-Jung Kwon, et al. · IEEE Transactions on Circuits & Systems II Express Briefs · 14
Low-voltage, high-speed circuit designs for gigabit DRAMs
1997 · Kyuchan Lee, Changhyun Kim, et al. · IEEE Journal of Solid-State Circuits · 13
A 1 Gbit synchronous dynamic random access memory with an independent subarray-controlled scheme and a hierarchical decoding scheme
1998 · Kyuchan Lee, Changhyun Kim, et al. · IEEE Journal of Solid-State Circuits · 1
Works count: 4
Citation count: 52
H-index: 3
I10-index: 3
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