Work

A 2.5-V, 333-Mb/s/pin, 1-Gbit, double-data-rate synchronous DRAM

Year: 1999

Type: article

Source: IEEE Journal of Solid-State Circuits

DOI: 10.1109/4.799867

Authors: Hongil Yoon, Gi-Won Cha, Changsik Yoo, Nam-Jong Kim, Keum-Yong Kim, Chang Ho Lee, Kyu-Nam Lim, Kyuchan Lee, Jun-Young Jeon, Tae Sung Jung, Hongsik Jeong, Tae-Young Chung, Kinam Kim, Soo In Cho

Institutions: Samsung Electronics (South Korea), Samsung (South Korea), ETH Zurich, Integrated Systems Laboratory

Language: English

Topic: Low-power high-performance VLSI design

Subfield: Electrical and Electronic Engineering

Field: Engineering

Domain: Physical Sciences

SDG: Industry, innovation and infrastructure

Open Access status: closed

OpenAlex ID: W2129448581

FWCI: 2.993

Cites: 12

Cited by: 24

Related to: 10