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Taeyoung Chung

Observed names: T. Chung, T.Y. Chung, Tae-Young Chung
ORCID: 0000-0003-0514-2975
Observed ORCID: 0000-0003-0514-2975
OpenAlex ID: A5045565898
Anomalous junction leakage current induced by STI dislocations and its impact on dynamic random access memory devices
1999 · Daewon Ha, Changhyun Cho, et al. · IEEE Transactions on Electron Devices · 54
A Wideband CMOS Noise-Canceling Low-Noise Amplifier With High Linearity
2015 · Taeyoung Chung, Hankyu Lee, et al. · IEEE Microwave and Wireless Components Letters · 50
A cost effective embedded DRAM integration for high density memory and high performance logic using 0.15 μm technology node and beyond
2000 · Daewon Ha, Dongwon Shin, et al. · IEEE Transactions on Electron Devices · 24
A 2.5-V, 333-Mb/s/pin, 1-Gbit, double-data-rate synchronous DRAM
1999 · Hongil Yoon, Gi-Won Cha, et al. · IEEE Journal of Solid-State Circuits · 24
Optical properties of ZnSSe/ZnMgSSe quantum wells
1997 · Tae-Young Chung, J H Oh, et al. · Semiconductor Science and Technology · 23
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Fully Integrated 56 nm DRAM Technology for 1 Gb DRAM
2007 · Y.K. Park, S.H. Lee, et al. · Symposium on VLSI Technology · 13
Local-damascene-finFET DRAM integration with p/sup +/ doped poly-silicon gate technology for sub-60nm device generations
2005 · Yong-Sung Kim, Eun-Cheol Lee, et al. · Technical digest - International Electron Devices Meeting/Technical digest · 12
Exciton binding energies in GaN/AlGaN quantum-well structures
1998 · Tae-Young Chung, K J Chang · Semiconductor Science and Technology · 12
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A 0.13 μm DRAM technology for giga bit density stand-alone and embedded DRAMs
2002 · K.N. Kim, T.Y. Chung, et al. · Symposium on VLSI Technology · 10
Fabrication and Electrical Properties of Local Damascene FinFET Cell Array in Sub-60㎚ Feature Sized DRAM
2006 · Yong‐Sung Kim, Soo-Ho Shin, et al. · 8
Highly manufacturable 90 nm DRAM technology
2003 · Y.K. Park, C.H. Cho, et al. · Technical digest - International Electron Devices Meeting/Technical digest · 7
Investigation of pMOSFET Hot Electron Induced Punch Through (HEIP) in Shallow Trench Isolation
2001 · Jae-kyu Lee, Sang-hyeon Lee, et al. · European Solid-State Device Research Conference · 5
A novel method to analyze and design a NWL scheme DRAM
2008 · Seokhan Park, Bonggu Sung, et al. · IEEE International Reliability Physics Symposium proceedings · 4
The abnormality in gate oxide failure induced by stress-enhanced diffusion of polycrystalline silicon
2002 · Yongseok Ahn, Sanghyun Lee, et al. · Microelectronics Reliability · 4
Data Retention Time and Electrical Characteristics of Cell Transistor According to STI Materials in 90 ㎚ DRAM
2003 · Sangchul Shin, S.H. Lee, et al. · JSTS Journal of Semiconductor Technology and Science · 3
Junction-to-top and junction-to-board thermal resistance measurement for 119 BGA packages
2003 · T. Chung, M. Kim, et al. · Annual IEEE Semiconductor Thermal Measurement and Management Symposium/Proceedings · 3
A DRAM technology using MIM BST capacitor for 0.15 /spl mu/m DRAM generation and beyond
1999 · K.N. Kim, D.H. Kwak, et al. · Symposium on VLSI Technology · 3
A 10A/μs Fast Transient AOT Voltage Regulator on DDR5 DIMM with Dithered Pseudo-Constant Switching Frequency Achieving -6dB Harmonic Suppression
2021 · Taeyoung Chung, Sooa Kim, et al. · Symposium on VLSI Circuits · 2
A novel thin BOX SOI technology using bulk Si wafer for system-on-chip (SoC) application
2006 · Chang Woo Oh, Hyun Jun Bae, et al. · Symposium on VLSI Technology · 2
A novel cell-STP (storage node through plate node) cell-technology for multigigabit-scale DRAM and logic-embedded DRAM generations
2003 · H.S. Uh, S.H. Song, et al. · Technical digest - International Electron Devices Meeting/Technical digest · 2
Highly Extendible Memory Cell Architecture for Reliable Data Retention Time for 0.10mm Technology Node and beyond
2002 · Jaegoo Lee, Changhyun Cho, et al. · European Solid-State Device Research Conference · 2
Novel Robust Structure and High k Dielectric Material for 90 ㎚ DRAM Capacitor
2003 · Y.K. Park, Y.S. Ahn, et al. · JSTS Journal of Semiconductor Technology and Science · 1
Improvement of data retention time using DRAM cell with metallic shield embedded (MSE)-STI for 90nm technology node and beyond
2003 · S.H. Lee, S.H. Hong, et al. · 1
A Novel DRAM Technology using Dual Spacer and mechanically Robust Capacitor for 0.12um DRAM and beyond
2001 · Jaegoo Lee, Jinwoo Lee, et al. · European Solid-State Device Research Conference · 1
A Novel Cell Structure with Bit Line Cap Spacer (BCS) and Top Enlarged Storage Node Contact (TESC) for 90 nm DRAM Technology and Beyond
2004 · C.J. Yun, Y.K. Park, et al. · International Conference on Solid State Devices and Materials (SSDM)
Works count: 31
Citation count: 270
H-index: 9
I10-index: 9
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