Author

K. Aoyama

Observed institution: Sony (Japan)

OpenAlex ID: A5020249140

A 1.4 ns access 700 MHz 288 kb SRAM macro with expandable architecture

2003 · H. Shimizu, K. Ijitsu, et al. · Digest of technical papers/Digest of technical papers - IEEE International Solid-State Circuits Conference · 13

A 500 MHz 288 kb CMOS SRAM macro for on-chip cache

2002 · K. Furumochi, H. Shimizu, et al. · Digest of technical papers/Digest of technical papers - IEEE International Solid-State Circuits Conference · 12

5.4 GOPS linear array architecture DSP for video-format conversion

2002 · M. Kurokawa, A. Hashiguchi, et al. · Digest of technical papers/Digest of technical papers - IEEE International Solid-State Circuits Conference · 7

Video DSP architecture and its application design methodology for sampling rate conversion

2002 · K. Nakamura, M. Kurokawa, et al. · SiPS ... design and implementation - IEEE Workshop on Signal Processing Systems · 4

5. 4 GOPS, 81 GB/s Linear Array Architecture DSP

1998 · A. Hashiguchi, M. Kurokawa, et al. · IEICE Transactions on Electronics · 2

FP 15.7: 5.4GOPS Linear Array Architecture DSP for Video-Format Conversion

1996 · M. Kurokawa, A. Hashiguchi, et al. · 1

High quality multi-scan converter for XGA-LCD projector by video DSP

2002 · K. Aoyama, A. Shimizu, et al. · International Conference on Consumer Electronics

High Quality Multi-scan Converter for XGA-LCD Projector

2000 · Video Dsp, K. Aoyama, et al.

700MHz 288kb SRAM Macro with Expandable Architecture

1999 · Haruo Shimizu, K. Ijitsu, et al. · 電子情報通信学会技術研究報告. ICD, 集積回路

Works count: 9

Citation count: 39

H-index: 4

I10-index: 2